Semiconductor device for executing fuzzy inference and method of operation thereof

• US 5,299,283 A
• Filed: 01/03/1991
• Issued: 03/29/1994
• Est. Priority Date: 01/29/1990
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hamamoto, Takeshi
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/638,722
• Time in Patent Office: 1,181 Days
• Field of Search: 395/425, 395/3, 395/21, 395/61, 395/900, 365/49, 364/715.01, 364/715.06
• US Class Current: 706/4
• CPC Class Codes: G06N 7/04 Physical realisation
• CPC Class Codes: Y10S 706/90 Fuzzy logic
• CPC Class Codes: Y10S 706/919 Designing, planning, programming, CAD, CASE

Abstract

A device for executing fuzzy inference includes a first storage area constituting a condition portion of a fuzzy set and a second storage area constituting a conclusion portion of the fuzzy set. The first storage area stores membership functions of the condition portion in order to develop a first bit mapping while the second storage area stores membership functions of the conclusion portion in order to develop a second bit mapping. Each of the first and second storage areas has X addresses which are designated by an input signal and Y addresses which are designated by a membership value. The device further includes circuitry for detecting corresponding rows of the first and second storage areas on which signal potentials are both a logical true after application of input signals to the first and second storage areas, other circuitry for detecting a Y address specifying a highest-order row among the detected rows, and additional circuitry for deriving a membership value in accordance with the detected Y address. The first and second storage areas preferably each include an array of content addressable memory cells having X addresses applied by an input pattern. A row detecting circuit detects coincidence/non-coincidence of signal potentials on coincidence detection lines of the content addressable memory cell arrays. The construction realizes a device for executing a fuzzy inference which is not limited by the number of rules or inputs and executes MIN-MAX operations at a high speed.

Claims

1. A semiconductor device, comprising:

a first storage area for storing first data representing a first relationship between a first input signal and a first output signal, said first storage area including a plurality of content addressable memory cells disposed in columns and rows for storing said first data in order to develop a first bit mapping, the first input signal being input to said first storage area and representing a first input data pattern to be compared with said first data while the first output signal specifies addresses of said plurality of content addressable memory cells of said first storage area in which coincidence is detected between said first input data pattern and said first data stored in said first storage area;

a second storage area including a plurality of content addressable memory cells disposed in rows and columns for storing second data in order to develop a second bit mapping, said second data representing a second relationship between a second input signal and a second output signal, the second input signal being input to said second storage area as a second input data pattern to be compared with said second data while the second output signal specifies addresses of said plurality of content addressable memory cells of said second storage area in which coincidence is detected between said second input data pattern and said second data stored in said second storage area;

coincidence detection signal lines for said first storage area and said second storage area, the coincidence detection signal lines of said first storage area being provided in a one-to-one corresponding relationship to the coincidence detection signal lines of said second storage area, a signal potential on each coincidence detection signal line representing one of coincidence and non-coincidence; and

means responsive to the signal potentials on said coincidence detection signal lines in said first and second storage areas after the first and second input signals are input as said first and second input data patterns into said first and second storage areas, respectively, for specifying those of said coincidence detection signal lines which indicate coincidence and for determining a magnitude relationship between the first and second output signals.

2. A semiconductor device according to claim 1, wherein the first and second storage areas are formed in a common storage array and corresponding rows of said first and second storage areas have the same coincidence detection signal lines.

3. A semiconductive device according to claim 2, wherein

said semiconductor device executes a fuzzy inference,

said first storage area stores a fuzzy set condition portion and said second storage area stores a fuzzy set conclusion portion,

said first and second data represent membership values for different rules and different types of the first and the second input signals, and the membership values are cyclically stored in a predetermined order respectively in said first and second storage areas such that the rules and types of the first input

signal associated with stored membership values represented by the first data correspond to those of the second input signal associated with stored membership values represented by the second data, and

the first and second output signals provide membership values.

4. A semiconductor device according to claim 2, wherein said means for specifying and determining includes a plurality of latching means coupled to said coincidence detection signal lines for detecting and latching the signal potentials on said coincidence detection signal lines as data bits, highest-order row detecting means responsive to latched data bits of said plurality of latching means for detecting the highest-order bit position of data bits indicating coincidence between said first input data pattern and said first data and also between said second input data pattern and said second data, and for outputting a row address corresponding thereto, and means responsive to said row address output from said highest-order row detecting means for deriving a membership value of a final output.

5. A semiconductor device according to claim 4, wherein said highest-order row detecting means includes a plurality of first logical gates each having a false input and a true input and outputting a logical product of signals received at respective false and true inputs, said plurality of first logical gates respectively coupled to said plurality of latching means, each of said first logical gates receiving, at its false input, latched data from a corresponding one of said plurality of latching means and receiving, at its true input, an output of an adjacent higher order first logical gate, one of said plurality of first logical gates receiving at its true input a signal fixed to the logical true which corresponds to the highest-order bit position of said data bits, and a plurality of second logical gates, each of said plurality of second logical gates being connected to receive, at one input thereof, latched data from a corresponding latching means and receive, at another input thereof, an output of an adjacent higher order first logical gate to output a logical product output signal.

6. A semiconductor device according to claim 5, wherein said highest-order row detecting means further includes:

a plurality of output signal lines for outputting signals corresponding to an address in binary notation, each output signal line being coupled to a first reference potential;

a plurality of transistor groups, each transistor group including at least one transistor and each transistor of each transistor group being connected between a corresponding one of said plurality of output signal lines and a second reference potential, and controlled by the logical output signal of a corresponding one of said plurality of second logical gates, said address corresponding to the highest-order bit position of said data bits indicating coincidence between said first input data pattern and said first data and between said second input data pattern and said second data.

7. A semiconductor memory device for performing fuzzy inference, comprising:

a first memory array including a plurality of content addressable memory cells arranged in rows and columns, for storing first membership function data for first input data as an input variable in order to develop a first bit mapping;

a second memory array including a plurality of content addressable memory cells arranged in rows and columns, for storing second membership function data for second input data as an output variable in order to develop a second bit mapping, said first and second memory arrays having common rows;

first means for reading out data onto respective rows of said first and second memory arrays by supplying said first and second input data on the columns of said first and second memory arrays as retrieval data, respectively, the read out data representing one of either coincidence and noncoincidence between said first input data and said first membership function data and between said second input data and said second membership function data;

second means, respective to said first means, for detecting a most significant row address among the rows on which data read out by said first means indicate coincidence.

8. A method of executing fuzzy inference in a semiconductor device which includes a first storage area for storing first data representing a first relationship between a first input signal and a first output signal, said first storage area including a plurality of content addressable memory cells disposed in columns and rows and storing said first data in order to develop a first bit mapping, the first input signal being applied to said first storage area and representing a first input data pattern to be compared with said first data, a second storage area for storing second data representing a second relationship between a second input signal and a second output signal, said second storage area including a plurality of content addressable memory cells disposed in columns and rows and storing said second data in order to develop a second bit mapping, the second input signal being applied to said second storage area as a second input data pattern to be compared with said second data, and coincidence detection signal lines for said first and second storage areas, said first output signal specifying addresses of said plurality of content addressable memory cells of said first storage area in which coincidence is detected between said first input data pattern and said first data stored in said first storage area, and said second output signal specifying addresses of said plurality of content addressable memory cells of said second storage area in which coincidence is detected between said second input data pattern and said second data stored in said second storage area, said method comprising the steps of:

inputting the first input signal into said first storage area;

inputting the second input signal into said second first storage area;

detecting one of coincidence and non-coincidence between said first input data pattern and said first data, and between said second input data pattern and said second data and outputting resulting detection signals on said coincidence detection signal lines;

specifying addresses of those of said coincidence detection signal lines which indicates coincidence; and

determining the highest order address among the coincidence detection signal lines which indicate coincidence.