Network adapter using status inlines and data lines for bi-directionally transferring data between lan and standard p.c. parallel port

• US 5,299,314 A
• Filed: 09/08/1993
• Issued: 03/29/1994
• Est. Priority Date: 03/22/1990
• Status: Expired

• Current Assignee: Intel Corporation
• Original Assignee: Xircom Incorporated (Intel Corporation)
• Inventors: Gates, Dirk I.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Lim, Krisna
• Application Number:
  US08/117,990
• Time in Patent Office: 202 Days
• Field of Search: 395/200, 395/275, 395/800, 370/39
• US Class Current: 710/64
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2213/0004 Parallel ports, e.g. centronics

Abstract

A network adapter configured to functionally connect a local area network cable to a personal computer bus via the computer'"'"'s standard parallel port. The adapter includes a substantially fully enclosed housing having first and second external connectors respectively configured to mate with a computer'"'"'s parallel port connector and with a network cable. The adapter is primarily comprised of (1) network interface circuitry for transmitting data packets to and receiving data packets from a local area network and (2) input/output circuitry for bidirectionally transferring data bytes between the network interface circuitry and a computer'"'"'s parallel port.

Claims

1. A system for functionally connecting a personal computer to a local area network via the computer'"'"'s standard PC parallel port comprised of an external 25 pin D-shell connector, eight data lines, no more than five control out-lines, and no more than five status in-lines, each such data line, control out-line, and status in-line being electrically connected to a different one of said D-shell connector pins, said system comprising:

a network adapter having first connector means connected to said D-shell connector and second connector means connected to said network;

network interface means in said adapter connected to said second connector means for transmitting data packets to and receiving data packet from said network;

input/output circuit means in said adapter connected between said first connector means and said network interface means, said input/output means including control logic means responsive to signals on said D-shell connector pins connected to said control out-lines for selectively (1) transferring data bytes from said network interface means to said D-shell connector pins connected to said data lines and said status in-lines and (2) transferring data bytes from said D-shell connector pins connected to said data lines to said network interface means;

software driver means executable by said computer for determining whether said parallel port is configured for bidirectional or unidirectional data transfer; and

means for configuring said control logic means to transfer data bytes to said pins connected to said data lines when said parallel port is configured for bidirectional data transfer and to said status lines when said parallel port is configured for unidirectional data transfer.

2. The system of claim 1 wherein said input/output circuit means is selectively operable in either a full data byte transfer mode or a partial data byte transfer mode;

and

means for causing said input/output circuit means to operate in said full byte transfer mode when said parallel port is configured for bidirectional data byte transfer and in said partial byte transfer mode when said parallel port is configured for unidirectional data byte transfer.

3. The system of claim 2 wherein said input/output circuit means is operable in said partial byte transfer mode for sequentially supplying first and second data byte portions to said status in-lines.

4. The system of claim 3 wherein said input/output circuit means includes signal shaping means for smoothing level transitions of signal inputs from said parallel port.

5. The system of claim 4 wherein said signal shaping means includes buffer means for smoothing out perturbations in said signal level transitions.

6. The system of claim 5 wherein said single shaping means includes digital debouncing means for removing spikes in said signal level transitions having a duration less than 500 nanoseconds.

7. The system of claim 1 wherein said network adapter comprises:

a housing having said network interface means and input/output circuit means internally mounted therein; and

wherein

said first connector means is externally mounted on said housing for removable connection to said parallel port external connector.

8. The system of claim 7 wherein said second connector means is externally mounted on said housing for removable connection to said network.

9. The system of claim 8 wherein said housing is dimensioned to be conveniently carried by a user having a length less than 8.0 inches, a width less than 3.5 inches and a height less than 2.0 inches.

10. The system of claim 3 wherein a full data byte to be transferred to said parallel port is comprised to eight bits respectively represented as 7,6,5,4,3,2,1,0;

and wherein

said first data byte portion includes bits 7,5,4 and 3 and said second data byte portion includes bits 6,2,1, and 1.

11. The system of claim 10 further including said personal computer;

and

means controlling said computer for reassembling said first and second data byte portions sequentially supplied to said status input lines for form a full data byte.

12. The system of claim 11 wherein said means controlling said computer includes means for transferring the four bits of each successive data byte portion into stages 7,5,4, and 3 of an eight bit register where the stages from most to least significant are numbered 7,6,5,4,3,2,1,0.

13. A network adapter configured to functionally connect a local area network cable to an internal bus of a personal computer (PC) via a standard PC parallel port comprised of an external 25 pin D-shell connector, eight data lines, no more than five control out-lines, and no more than five status in-lines, each such data line, control out-line, and status in-line being electrically connected to a different one of said D-shell connector pins, said adapter comprising:

a housing;

first connector means mounted externally on said housing configured for connecting to said D-shell connector;

second connector means mounted externally on said housing configured for connecting to said network cable;

network interface means mounted in said housing connected to said second connector means for transmitting data packets to and receiving data packets from said network cable; and

input/output means mounted in said housing connected between said first connector means and said network interface means, said input/output means including control logic means responsive to signals on said D-shell connector pins connected to said control out-lines for selectively (1) transferring data bytes from said network interface means to said D-shell connector pins connected to said status in-lines and (2) transferring data bytes from said D-shell connector pins connected to said data lines to said network interface means.

14. The network adapter of claim 13 wherein said control logic means is additionally responsive to signals on said D-shell connector pins connected to said control out-lines for selectively transferring data bytes from said network interface means to said D-shell connector pins connected to said data lines.

15. The network adapter of claim 14 wherein said control logic means is capable of being programmed by a PC via its parallel port to which the adapter is connected.

16. The network adapter of claim 13 wherein said housing is dimensioned to be conveniently carried by a user having a length less than 8.0 inches, a width less than 3.5 inches and a height less than 2.0 inches.

17. A method of communicating data between a personal computer having an internal bus and a standard PC parallel port, comprised of an external 25 pin D-shell connector, eight data lines, no more than five control out-lines, and no more than five status in-lines, each such data line, control out-line, and status in-line being electrically connected to a different one of said D-shell connector pins, and a network including a network medium, said method comprising:

connecting a transceiver to said network medium;

controlling said transceiver to transmit data packets from a data packet memory to said network medium and to receive data packets from said network medium for storage in said memory;

connecting input/output circuitry to said D-shell connector; and

controlling said input/output circuitry in response to signals on said D-shell connector pins connected to said control out-lines for selectively (1) transferring data bytes from said transceiver to said internal bus via said D-shell connector pins connected to said status in-lines and (2) transferring data bytes from said internal bus via said D-shell connector pins connected to said data lines to said transceiver.

18. The method of claim 17 wherein said step of connecting said input/output circuitry to said parallel port includes the step of detachably mating a multipin connector fixed to said input/output circuitry to said parallel port D-shell connector.

19. The method of claim 18 wherein said step of detachably mating includes the further step of threading at least one screw into a threaded hole mounted adjacent to said D-shell connector.

20. The method of claim 17 wherein said step of controlling said input/output circuitry includes a step of determining whether said parallel port is configured for bidirectional data transfer.

21. The method of claim 17 wherein said step of transferring data bytes to said computer internal bus via said status in-lines includes the substeps of sequentially transferring partial bytes.

22. The combination with network interface circuitry adapted to be connected to a local area network medium, wherein said network interface circuitry includes a memory for storing data received from and to be transmitted to said network medium, input/output circuitry for connecting a personal computer (PC) having an internal bus and a standard PC parallel port to said network interface circuitry, said parallel port being comprised of an external 25 pin D-shell connector, eight data lines, no more than five control out-lines, and no more than five status in-lines, each such data line, control out-line, and status in-line being electrically connected to a different one of said D-shell connector pins, said input/output circuitry including:

a multipin connector fixed to said input/output circuitry;

means for detachably connecting said multipin connector to said D-shell connector; and

control logic means for bidirectionally transferring data between said internal bus and said memory via said multipin connector and said parallel port D-shell connector, said control logic means being responsive to signals on said D-shell connector pins connected to said control out-lines for selectively (1) transferring data bytes from said network interface means to said D-shell connector pins connected to said data lines and said status in-lines and (2) transferring data bytes from said D-shell connector pins connected to said data lines to said network interface means.

23. The combination of claim 22 including captive screw means mounted on said housing for threaded engagement with screw holes adjacent to said D-shell connector.

24. The combination of claim 22 wherein said parallel port defines unidirectional data out-lines and unidirectional status in-lines;

and wherein

said control logic means transfers data from said internal bus to said memory via said data out-lines and from said memory to said internal bus via status in-lines.

25. The combination of claim 22 wherein said network interface circuitry is configured to implement the IEEE 802 standard.

26. Apparatus for transmitting data to and receiving data from a local area network and for bidirectionally transferring such data to a computer'"'"'s internal bus via the computer'"'"'s standard parallel port comprised of an external 25 pin D-shell connector, eight data lines, no more than five control out-lines, and no more than five status in-lines, each such data line, control out-line, and status in-line being electrically connected to a different one of said D-shell connector pins, said apparatus including:

a housing;

network interface circuitry mounted in said housing including a data packet memory and transceiver means for transmitting data from said memory to said network and for receiving data from said network for storage in said memory;

a multipin connector externally mounted on said housing configured for detachable connection to said parallel port connector; and

input/output circuitry mounted in said housing including control logic means for bidirectionally transferring data bytes between said memory and said internal bus via said external multipin connector and said parallel port connector, said control logic means being responsive to signals on said D-shell connector pins connected to said control out-lines for selectively (1) transferring data bytes from said network interface means to said internal bus via said D-shell connector pins connected to said status in-lines and (2) transferring data bytes from said internal bus via said D-shell connector pins connected to said data lines to said network interface circuitry.

27. The apparatus of claim 26 wherein said D-shell connector has threaded holes located proximate thereto;

and wherein

said external multipin connector is configured for detachable mating to said D-shell connector; and

wherein

at least one screw is mounted on said housing and configured for threaded coupling into one of said threaded holes to secure said connectors in mating relationship.

28. The apparatus of claim 26 wherein said control logic means includes a gate array capable of being programmed in response to information supplied thereto from said computer internal bus via said parallel port connector.

29. The apparatus of claim 26 wherein said control logic means transfers data from said internal bus to said memory via a first set of connecting pins in said external multipin connector and said parallel port connector and from said memory to said bus via a second set of connecting pins in said connectors.

30. The apparatus of claim 26 wherein said network interface circuitry is configured to implement the IEEE 802 standard.