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Personal computer with programmable threshold FIFO registers for data transfer

  • US 5,299,315 A
  • Filed: 09/17/1992
  • Issued: 03/29/1994
  • Est. Priority Date: 09/17/1992
  • Status: Expired due to Fees
First Claim
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1. A personal computer system comprising:

  • a high speed data bus,an input/output data bus,a plurality of bus master devices each coupled directly to one corresponding one of two busses, namely (i) said high speed data bus and (ii) said input/output data bus, for transferring data through said one corresponding one of two busses, one of said bus master devices being a microprocessor coupled directly to said high speed data bus and functioning as a system central processing unit,a bus interface controller coupled directly to both of said high speed data bus and said input/output data bus for providing communications between said high speed data bus and said input/output data bus, said bus interface controller (i) providing for arbitration among such ones of said bus master devices as are directly coupled to said high speed data bus for access to said high speed data bus and (ii) further providing for arbitration among said high speed data bus and such ones of said bus master devices as are directly coupled to said input/output bus for access to said input/output data bus, andone of said bus master devices other than said microprocessor having a data FIFO register operatively connected between said one other bus master device and a corresponding one of said high speed data bus and said input/output data bus to which said one other bus master device is directly coupled for passing data therebetween and also having a threshold register, said threshold register for receiving from said FIFO register bits indicating a threshold fill level of said FIFO register required before arbitration through said bus interface controller will be sanctioned.

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