Personal computer with programmable threshold FIFO registers for data transfer

• US 5,299,315 A
• Filed: 09/17/1992
• Issued: 03/29/1994
• Est. Priority Date: 09/17/1992
• Status: Expired due to Fees

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Eleazar-Garcia, Serafin J. Jr., Chin, Arthur L., Keener, Don S., Moore, Gregory J., Lee, Timothy V., Stine, Eric S.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): MEKY, MOUSTAFA M
• Application Number:
  US07/947,013
• Time in Patent Office: 558 Days
• Field of Search: 395/250, 395/425, 364/228.5, 364/229.2, 364/238.2, 364/238.3, 364/238.4, 364/238.6, 364/239.6, 364/239.7, 364/239.8, 364/240.5, 364/242.6, 364/242.92 , 364/242.93
• US Class Current: 710/110
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

Claims

1. A personal computer system comprising:

a high speed data bus,

an input/output data bus,

a plurality of bus master devices each coupled directly to one corresponding one of two busses, namely (i) said high speed data bus and (ii) said input/output data bus, for transferring data through said one corresponding one of two busses, one of said bus master devices being a microprocessor coupled directly to said high speed data bus and functioning as a system central processing unit,

a bus interface controller coupled directly to both of said high speed data bus and said input/output data bus for providing communications between said high speed data bus and said input/output data bus, said bus interface controller (i) providing for arbitration among such ones of said bus master devices as are directly coupled to said high speed data bus for access to said high speed data bus and (ii) further providing for arbitration among said high speed data bus and such ones of said bus master devices as are directly coupled to said input/output bus for access to said input/output data bus, and

one of said bus master devices other than said microprocessor having a data FIFO register operatively connected between said one other bus master device and a corresponding one of said high speed data bus and said input/output data bus to which said one other bus master device is directly coupled for passing data therebetween and also having a threshold register, said threshold register for receiving from said FIFO register bits indicating a threshold fill level of said FIFO register required before arbitration through said bus interface controller will be sanctioned.

2. A personal computer system according to claim 1 wherein said system further comprises storage memory devices for nonvolatile storage of data, and wherein said plurality of bus master devices further includes a storage controller coupled directly to said high speed data bus and to said storage memory devices for regulating communications with said storage memory devices.

3. A personal computer system according to claim 1 wherein said plurality of bus master devices further includes an input/output controller.

4. A personal computer system according to claim 1 wherein said plurality of bus master devices further includes a digital signal processor.

5. A person computer system according to claim 1 wherein said plurality of bus master devices further includes a video signal processor.

6. A personal computer system comprising:

a high speed data bus;

a microprocessor coupled directly to said high speed data bus;

volatile memory coupled directly to said high speed data bus for volatile storage of data;

storage memory devices for nonvolatile storage of data;

a storage controller coupled directly to said high speed data bus and to said storage memory devices for regulating communications with said storage memory devices;

an input/output data bus;

an input/output controller coupled directly to said input/output data bus;

a digital signal processor coupled directly to said input/output data bus;

a video signal processor coupled directly to said input/output data bus; and

a bus interface controller coupled to said high speed data bus and to said input/output data bus for providing communications between said high speed data bus and said input/output data bus, said bus interface controller providing for arbitration among said microprocessor and said storage controller coupled directly to said high speed data bus for access to said high speed data bus, and providing for arbitration among said input/output controller and said digital signal processor and said video signal processor coupled directly to said input/output data bus and said high speed data bus for access to said input/output data bus,

at least one of said storage controller and said input/output controller and said digital signal processor and said video signal processor having a data FIFO register operatively connected between the corresponding one of said input/output controller and said digital signal processor and said video signal processor and the corresponding one of said busses for passing data therebetween and also having a threshold register for receiving bits indicating a threshold fill level of said FIFO register required before arbitration through said bus interface controller will be sanctioned.