Parallel processing device to operate with parallel execute instructions

• US 5,299,321 A
• Filed: 07/26/1993
• Issued: 03/29/1994
• Est. Priority Date: 12/18/1990
• Status: Expired due to Term

• Current Assignee: Gromens Acquisitions Co LLC (Intellectual Ventures LLC)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Iizuka, Hiroshi
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/097,325
• Time in Patent Office: 246 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/200, 395/375, 395/700, 395/800
• US Class Current: 712/212
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A parallel processing device consists of plural processing pipelines arranged in parallel, decoders which decode processing instructions and outputs them to respective processing pipelines, and a general register in which the processing instruction to be outputted to each of decoders is written in one of its registering sections, or a multiple-port register. The processing instructions are written in the general register or the multiple-port register, wherein the respective registering sections storing the processing instructions are simultaneously specified either by a parallel instruction device, a one-dimensional expanded instruction register, or a two-dimensional expanded instruction register so that their contents are simultaneously outputted to make each of the processing pipelines perform simultaneously. Thus, the simultaneous concentration of a large amount of information can be avoided during the parallel processing operation, eliminating the need for a bus with a large bit number.

Claims

1. A parallel processing device for performing processing operations in response to processing instructions defined by a parallel execute instruction to be executed in parallel, comprising:

an input circuit to receive the processing instructions and data to be processed;

a first decoder connected to said input circuit for decoding the processing instructions and producing a micro instruction for controlling processing corresponding to the decoded processing instructions;

storage circuitry to store at least either one of data to be processed and one of the processing instructions defined by the parallel execute instruction;

an internal bus connected to said input circuit and said storage circuitry for transferring bits of the data to be processed and the processing instructions in parallel from said input circuit to said storage circuitry;

a plurality of second decoders connected to said storage circuitry, each second decoder decoding a respective instruction received from said storage circuitry, and producing a micro instruction for controlling processing corresponding to the instruction decoded therein;

a plurality of parallel pipeline processors, each connected to said storage circuitry and each except one to a respective one of said second decoders, said parallel pipeline processors being connected to said internal bus, whereby each parallel processor except one performs processing operations in response to the micro instruction received corresponding second decoder; and

a multiplexer interconnected to said first decoder, to at least one of said second decoders that is not connected to any of said parallel pipeline processors, and to said parallel pipeline processor that is not connected to said second decoder, said multiplexer selectively connecting either of said first decoder and said second decoder connected thereto to said parallel pipeline processor connected thereto;

whereby the micro instruction received from said first decoder is transferred over said internal bus to said storage circuitry sequentially on an instruction basis to be stored therein.

2. A device in accordance with claim 1, wherein said storage circuitry comprises a general register for storing therein either one of data to be processed and the processing instruction, the parallel instruction including a plurality of fields, each said field containing an operand designating one of said plurality of parallel pipeline processors.

3. A device in accordance with claim 1, wherein said input circuit comprises:

instruction storage means connected to said first decoder means and said internal bus for storing the processing instructions therein; and

data storage means connected to said internal bus for storing the data to be processed.

4. A device in accordance with claim 1, wherein said internal bus comprises a plurality of bit lines corresponding in number to the number of bits of the data to be processed or the processing instructions.

10. The device of claim 1 wherein

said second decoders include first through n-th decoders;

said parallel pipeline processors include first through n-th processing pipelines;

each of said parallel first through n-th decoders is connected to a corresponding one of said first through n-th processors.

5. A parallel processing device for performing processing operations in response to processing instructions defined by a parallel execute instruction to be executed in parallel, comprising:

an input circuit to receive the processing instructions and data to be processed;

an instruction decoder connected to said input circuit to decode the processing instructions and to provide a micro instruction for controlling processing corresponding to decoded processing instructions;

first register circuitry for storing therein data to be processed;

an internal bus connected to said input circuit and said first register circuitry for transferring bits of the data in parallel from said input circuit to said first register circuitry;

second register circuitry connected to said instruction decoder for storing the micro instruction for controlling processing corresponding to the decoded processing instructions;

third register circuitry connected to said instruction decoder and said second register circuitry for storing either of a processing instruction not defined by the parallel execute instruction and a decode instruction to define a selected portion of said second register circuitry;

a multiplexer connected to said third register circuitry and said selected portion of said second register circuitry for selecting an output from either of said third register circuitry and said second register circuitry; and

a plurality of parallel pipeline processors connected to said first register circuitry, one of said parallel pipeline processors being connected to an output of said multiplexer, and the rest of said parallel pipeline processors being connected to said second register circuitry, except said selected portion of said second register circuitry, said parallel pipeline processors being connected to said internal bus, said parallel processors being effective to execute parallel processing operations in response to the micro instruction provided from said second register circuitry, one of said parallel pipeline processors being effective to execute parallel processing operations in response to an output of said multiplexer;

said instruction decoder decoding the processing instruction, which is not defined by the parallel execute instruction, to store the micro instruction for controlling processing produced in said third register circuitry while said multiplexer selects the output from said third register circuitry;

said instruction decoder being operative in response to the decode instruction to store the decode instruction in said third register circuitry, and decoding the processing instructions which are defined by the parallel execute instruction, to store the micro instructions for controlling processing produced in said second register circuitry, while said multiplexer selects the output from said selected portion of said second register circuitry.

6. A device in accordance with claim 5, wherein said first register circuitry includes a multi-port register having storage positions in each of which data is stored.

7. A device in accordance with claim 6, wherein said internal bus comprises bit lines corresponding in number to the number of bits of the data.

8. A device in accordance with claim 5, wherein said second register circuitry is aligned logically and unidimensionally, the decode instruction including a field containing a destination operand designating a selected portion of said second register circuitry.

9. A device in accordance with claim 5, wherein said second register circuitry is aligned logically and bidimensionally, a decode instruction including a first field which contains a destination operand designating a column, and a second field which contains another destination operand designating a line of said second register circuitry.