Method of making staggered gate MOSTFT

• US 5,300,446 A
• Filed: 05/05/1993
• Issued: 04/05/1994
• Est. Priority Date: 05/08/1992
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Fujioka, Toshio
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/057,747
• Time in Patent Office: 335 Days
• Field of Search: 437/41, 437/44, 437/40, 437/913, 437/915, 437/208, 437/56, 437/58, 148/DIG. 105, 148/DIG. 106
• US Class Current: 438/158
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: Y10S 148/105 Masks, metal
• CPC Class Codes: Y10S 148/106 Masks, special
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

On an insulating film (12) covering the surface of a semiconductor substrate (10), a gate electrode layer (14), a gate insulating film (16), and a semiconductor layer (18) such as silicon are sequentially deposited to form an under-gated MOS transistor. A flat coating film such as resist is formed covering the semiconductor layer (18). The coating film is then etched back to expose the surface of the semiconductor layer (18) at the area above the gate electrode layer (14). The left coating film is used as the mask for the selective growth of a mask material layer (24) such as tungsten on the exposed surface of the semiconductor layer (18) with a side-projection. After removing the left coating film, impurity ions such as BF2 are selectively injected in the semiconductor layer (18) using the mask material layer (24) as the mask to form a source region (18S) and a drain region (18D).

Claims

1. A method of manufacturing an under-gated semiconductor device comprising the steps of:

forming a gate electrode layer on an insulating surface of a substrate;

forming a gate insulating film covering said gate electrode layer;

forming a semiconductor layer on said gate insulating film to overlie said gate electrode layer;

forming a flat coating film covering said semiconductor layer;

etching back said coating film to partially expose a surface of said semiconductor layer at an area overlying said gate electrode layer and to leave said coating film at two side areas of the exposed surface;

selectively growing a mask material layer on the exposed surface of said semiconductor layer with a side-projection, by using said left coating film as a mask; and

removing said left coating film and selectively injecting impurity ions in said semiconductor layer to form an impurity doped source region and an impurity doped drain region at opposite sides of said gate electrode region, by using said mask material layer as an ion injection mask.

2. A method according to claim 1, wherein said mask material layer is made of tungsten.

3. A method according to claim 1, wherein the selective growth of said mask material layer is performed by chemical vapor deposition.

4. A method according to claim 3, wherein said chemical vapor deposition is performed by using a reduction reaction of tungsten hexafluoride with silicon.

5. A method according to claim 3, wherein said chemical vapor deposition is performed under an application of light.

6. A method according to claim 1, wherein said injected ions are BF₂ ions.