High voltage thin film transistor having a linear doping profile and method for making

• US 5,300,448 A
• Filed: 02/08/1993
• Issued: 04/05/1994
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L., Arnold, Emil
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/015,061
• Time in Patent Office: 421 Days
• Field of Search: 148/DIG. 157, 437/40, 437/41, 437/21, 437/27, 437/38, 437/44, 437/74, 437/75, 437/909
• US Class Current: 438/163
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/861 Diodes

Abstract

The present invention is directed to a method and thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

Claims

1. In a method of manufacturing high voltage thin film transistors the steps comprising

(a) providing a thin layer of monocrystalline silicon over an oxide layer on a silicon substrate,

(b) decreasing resistivity of said thin layer of silicon by uniformly introducing impurities into said thin layer of silicon,

(c) forming a mask over said thin layer of silicon, said mask having a plurality of openings, each of said openings laterally increasing in dimension from that of a proceeding opening,

(d) introducing impurities into said thin layer of silicon through said plurality of openings to form a plurality of doped regions of different width,

(e) removing said mask, capping said thin layer of silicon with silicon nitride, and annealing to form a linear doping profile from said plurality of doped regions over a lateral distance of said thin layer of silicon, wherein said linear doping profile is formed with a minimum doping concentration at one end of said lateral distance and a maximum doping concentration at a second opposite end of said lateral distance,

(f) removing said silicon nitride at regions beyond edges of said lateral distance, thermally oxidizing exposed areas of said thin layer of silicon, and thereafter removing remaining portions of said silicon nitride, and

(g) forming a structure with said thin layer of silicon having said linear doping profile.

2. A method according to claim 1, wherein said annealing is carried out for a time ranging from 18 to 36 hours.

3. A method according to claim 2, wherein said annealing is carried out at a temperature of approximately 1150°

C.

4. A method according to claim 1, wherein said linear doping profile is formed with an effective dose given by

5. A method according to claim 1, wherein said lateral distance is formed to be at least 40-50 μ

m.

6. A method according to claim 4 wherein said step (g) is carried out to form a transistor structure by the steps of

(i) forming a polysilicon gate region over said thin layer at said one end of said lateral distance,

(ii) forming a source region in said thin layer at a side of said gate region opposite to said linear doping profile,

(iii) forming a drain region at said second opposite end of said lateral distance of said linear doping profile, and

(iv) forming electrical contacts to said source region, said gate region, and said drain region.

7. A method according to claim 1, wherein said step (b) is carried out by implanting ions.

8. A method according to claim 1, wherein said step (d) is carried out by implanting ions.

9. A method according to claim 8, wherein phosphorous ions are implanted an energy of about 100 keV and at an ion dose of about 2×

10¹³ /cm².

10. A method according to claim 6, wherein said concentration forms an increased breakdown voltage of said transistor structure ranging from about 700 V to about 900 V.

11. A method according to claim 10, wherein said increased breakdown voltage of said transistor structure is formed to approximately 800 V.