Process for fabricating sealed semiconductor chip using silicon nitride passivation film

• US 5,300,461 A
• Filed: 01/25/1993
• Issued: 04/05/1994
• Est. Priority Date: 01/25/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ting, Chiu H.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): HORTON, KENNETH
• Application Number:
  US08/008,469
• Time in Patent Office: 435 Days
• Field of Search: 437/226, 437/227, 437/228, 437/211, 437/215, 437/241, 156/634, 156/648
• US Class Current: 438/460
• CPC Class Codes: G11C 16/18 Circuits for erasing optically
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Claims

1. A process for forming a sealed computer chip comprising the steps of:

forming a plurality of electrical circuit devices on a silicon wafer having a silicon surface by the deposition of a plurality of device layers upon said silicon surface;

performing an etch step on said plurality of device layers, said etch step etching said device layers so as to expose a portion of said silicon surface, said etch step isolating said electrical circuit devices, each of said isolated electrical circuit devices forming a computer chip;

depositing a layer of passivation material over said silicon surface and over said computer chips, said layer of passivation material forming a seal over said silicon surface and said computer chips; and

selectively sawing portions of said silicon wafer so as to separate said computer chips.

2. The process for forming a sealed computer chip of claim 1 wherein said passivation layer comprises a thin layer of silicon nitride.

3. The process for forming a sealed computer chip of claim 2 wherein said layer of silicon nitride has on average thickness of less than 1000 angstroms.

4. The process for forming a sealed computer chip of claim 3 wherein said integrated circuit device includes a bonding pad, and wherein said process further comprises performing the following steps prior to the step of selectively sawing portions of said silicon wafer:

selectively etching at least some of that portion of said thin layer of silicon nitride passivation material which overlies said bonding pad, said etch being sufficient so as to allow for electrical contact to said bonding pad; and

selectively depositing a metal passivation layer over said etched portion of said thin layer of silicon nitride passivation material, said metal passivation layer comprising nickel.

5. The process for forming a sealed computer chip of claim 1 wherein a plurality of standard processing etch steps are performed on said device layers, and wherein said etch step further comprises the step of selectively etching a portion of each of said device layers during at least some of said standard processing etch steps.

6. The process for forming a sealed computer chip of claim 5 wherein said silicon nitride layer is a thin layer of silicon nitride which is transparent to ultraviolet light.

7. A process for forming a sealed semiconductor chip on a silicon wafer having a top surface comprising the steps of:

forming a number of device regions on said silicon wafer;

forming a plurality of device layers upon said silicon wafer such that said plurality of device layers overlie said device regions formed on said silicon substrate, said plurality of device layers including a bonding pad, said plurality of device layers contacting said device regions so as to form a plurality of integrated circuit devices;

etching said device layers so as to define a semiconductor chip upon said silicon wafer, said semiconductor chip including at least one of said integrated circuit devices, said chip having a top surface and a plurality of side surfaces, said etch of said device layers forming openings within said device layers so as to expose said bonding pad;

selectively depositing a metal passivation layer over said exposed area of said bonding pad, said metal passivation layer comprising nickel;

depositing a thin silicon nitride passivation layer over said silicon wafer and said semiconductor chip, said thin silicon nitride passivation layer deposited so as to overlie said top surface and said side surfaces of said semiconductor chip, and deposited so as to overlie said metal passivation layer, and

selectively etching at least some of that portion of said thin silicon nitride passivation layer which overlies said bonding pad, said etch being sufficient so as to allow for electrical contact to said bonding pad.

8. The process for forming a sealed semiconductor chip of claim 7 wherein said etch of said device layers comprises a plurality of standard processing etch steps.

9. The process for forming a sealed semiconductor chip of claim 7 wherein said silicon nitride passivation layer defines a top sealing surface, and wherein said metal passivation layer is selectively deposited so as to form a bump protruding from said top sealing surface.

10. The process for forming a sealed semiconductor chip of claim 7 wherein said silicon nitride passivation layer defines a top sealing surface, and wherein said metal passivation layer is selectively deposited so that said metal passivation layer does not extend over said top sealing surface of said silicon nitride passivation layer.

11. The process for forming a sealed semiconductor chip of claim 7 wherein said silicon nitride layer is a thin layer of silicon nitride which is transparent to ultraviolet light.