Semiconductor integrated circuit device having single-element type non-volatile memory elements

• US 5,300,802 A
• Filed: 05/20/1991
• Issued: 04/05/1994
• Est. Priority Date: 11/09/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kume, Hitoshi, Nishimoto, Toshiaki, Kamigaki, Yoshiaki, Komori, Kazuhiro, Meguro, Satoshi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/704,739
• Time in Patent Office: 1,051 Days
• Field of Search: 357/23.5, 357/23.6, 357/42, 257/315, 257/316, 257/321, 257/322
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Claims

1. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a plurality of memory cells each of which is constituted by a single field effect transistor, said memory cell comprising:

a control gate coupled to a word line;

a floating gate positioned under said control gate;

a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;

a second gate insulation film formed between the two gates;

source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type and said channel forming region being of a second conductivity type, said source region having a doping concentration which is higher than that of said drain region and which prevents surface depletion when high voltage is applied to said source region during an erasing operation of said memory, the junction depth of said source region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said drain region, and said first gate insulation film having a predetermined film thickness so as to permit tunneling of electrons from said floating gate, during the erasing operation of said memory, to said semiconductor substrate through said first gate insulation film; and

a semiconductor region of said second conductivity type formed in said semiconductor substrate and having a doping concentration higher than that of said channel forming region, said semiconductor region being brought into contact with said drain region at the channel forming region side thereof,

wherein said drain region operates as the drain of said single field effect transistor in both write and read modes of said EEPROM,

wherein said memory cell stores data when a first predetermined potential is applied to said drain region, and

wherein the data of said memory cell is read when a second predetermined potential is applied to said drain region, said second predetermined potential is lower in magnitude than said first predetermined potential.

2. A semiconductor integrated circuit device according to claim 1, wherein said first gate insulation film is a silicon oxide film which has a thickness about 100 angstrom.

3. A semiconductor integrated circuit device according to claim 2, wherein said first and second conductivity type are n-type and p-type, respectively.

4. A semiconductor integrated circuit device according to claim 3, wherein said EEPROM is flash type EEPROM.

5. A semiconductor integrated circuit device according to claim 1, wherein said semiconductor region of said second conductivity type is formed to surround both a channel side and the underside of said drain region.

6. A semiconductor integrated circuit device according to claim 5, wherein said drain region comprises a first region and a second region, both being of said first conductivity type, said second region being formed between said channel forming region and said first region, and wherein said semiconductor region of said second conductivity thereof is extended beneath said first and second regions and on the channel forming side of said second region.

7. A semiconductor integrated circuit device according to claim 6, wherein said source region includes a third region and a fourth region surrounding said third region, and wherein said third and fourth regions are formed in self-alignment with said controlling and floating gates thereof, and wherein there is further included side wall spacers along opposing commonly extending side walls of said controlling and floating gates, such that said first region is formed in self-alignment with a corresponding side wall spacer and said controlling and floating gates, and said second region is formed in self-alignment with said controlling and floating gates.

8. A semiconductor integrated circuit device according to claim 7, wherein said third region extends deeper into said semiconductor substrate than both said first and second regions.

9. A semiconductor integrated circuit device according to claim 8, wherein said first, second, third and fourth regions and said semiconductor region of said second conductivity type have depths, from the main surface of said semiconductor substrate, extending into said substrate of about 0.2 μ

m, 0.1 μ

m to 0.2 μ

m, 0.3 μ

m, 0.5 μ

m, and 0.3 μ

m to 0.5 μ

m, respectively.

10. A semiconductor integrated circuit device according to claim 9, wherein said FET is an n-channel type formed in a semi-conductor substrate of a p-conductivity type.

11. A semiconductor integrated circuit device according to claim 10, wherein said substrate includes a well region of a p-conductivity type wherein said FET is formed.

12. A semiconductor integrated circuit device according to claim 5, further comprising:

a data line being coupled to the drain region of said memory cell,

wherein said memory cell stores the data when said word line and said data line are respectively set to a third predetermined potential and to said first predetermined potential, each of which is higher than ground potential, and said memory erases the data in said memory cell when a fourth predetermined potential, which is higher than ground potential, is applied to said source region thereof.

13. A semiconductor integrated circuit device according to claim 12, wherein said third predetermined potential is higher in magnitude than said first predetermined potential and is of the same polarity thereof.

14. A semiconductor integrated circuit device having an electrically erasable programmable read only memory which includes a memory cell constituted by a single field effect transistor, said memory cell comprising:

a controlling gate coupled to a word line;

a floating gate positioned under said control gate;

a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;

a second gate insulation film formed between the two gates;

source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type and said semiconductor substrate being of a second conductivity type, said source region having a doping concentration higher than that of said drain region so as to prevent surface depletion when high voltage is applied to said source region at the time of an information erasing operation and said source region having a junction depth into said semiconductor substrate, with respect to said main surface thereof, greater than said drain region; and

a semiconductor region of said second conductivity type formed in said semiconductor substrate and having a doping concentration higher than that of said channel forming region, said semiconductor region being brought into contact with said drain region so as to enhance the intensity of an electric field in the vicinity of said drain region during an information writing operation of said memory cell,

wherein said drain region operates as the drain of said single field effect transistor in both write and read mode of said EEPROM,

wherein said memory cell stores data when a first predetermined potential is applied to said drain region, and

wherein the data of said memory cell is read when a second predetermined potential is applied to said drain region, said second predetermined potential is lower in magnitude than said first predetermined potential.

15. A semiconductor integrated circuit device according to claim 14, further comprising:

a data line being coupled to the drain region of said memory cell,

wherein said memory cell stores the data when said word line and said data line are respectively set to a third predetermined potential and to said first predetermined potential, each of which is higher than ground potential, and said memory erases the data in said memory cell when a fourth predetermined potential, which is higher than ground potential, is applied to said source region thereof.

16. A semiconductor integrated circuit device according to claim 15, wherein said third predetermined potential is higher in magnitude than said first predetermined potential and is of the same polarity thereof.

17. A semiconductor integrated circuit device according to claim 16, wherein said source region comprises a first region and a second region, both being of said first conductivity type, said second region being formed to surround both a channel side of said first region and the underside of said first region, and said second region having a doping concentration lower than that of said first region.

18. A semiconductor integrated circuit device according to claim 17, wherein said drain region comprises a third region and a fourth region, both being of said first conductivity type, said fourth region being formed between said channel forming region and said third region, and wherein said semiconductor region of said second conductivity type thereof consists of a fifth region extending to a depth beneath said third and fourth regions and on the channel forming side of said fourth region.

19. A semiconductor integrated circuit device according to claim 18, wherein said semiconductor substrate has a well region of a predetermined doping concentration and of said second conductivity type formed therein, and wherein said memory cell is disposed in said well region.

20. A semiconductor integrated circuit device according to claim 19, wherein said first and second regions are formed in self-alignment with said controlling and floating gates thereof, and wherein there is further included side wall spacers along opposing commonly extending side walls of said controlling and floating gates, such that said third region is formed in self-alignment with a corresponding side wall spacer and said controlling and floating gates, and said fourth region is formed in self-alignment with said controlling and floating gates.

21. A semiconductor integrated circuit device according to claim 20, wherein said first region extends deeper into said semiconductor substrate than both said third and fourth regions.

22. A semiconductor integrated circuit device according to claim 21, wherein said first region is heavily doped with arsenic (As) ions, said second region is doped with phosphorus (P) ions, said third region is heavily doped with As ions and said fourth region is a lightly doped region of As ions.

23. A semiconductor integrated circuit device according to claim 22, wherein said first, second, third, fourth and fifth regions have depths, from the main surface of said semiconductor substrate, extending in a direction into said well region thereof, of about 0.3 μ

m, 0.5 μ

m, 0.2μ

m, 0.1 μ

m to 0.2 μ

m and 0.3 μ

m to 0.5 μ

m, respectively.

24. A semiconductor integrated circuit device according to claim 17, wherein said first and second conductivity types are n-type and p-type, respectively, and wherein said field effect transistor (FET) is an n-channel type FET.

25. A semiconductor integrated circuit device according to claim 14, wherein said semiconductor region of said second conductivity type is formed so as to surround said drain region.

26. A semiconductor integrated circuit device according to claim 25, wherein said source region comprises a first region and a second region, both being of said first conductivity type, said second region being formed to surround a channel side of said first region and the underside of said first region, and said second region having a doping concentration lower than that of said first region and said drain region.

27. A semiconductor integrated circuit device according to claim 26, wherein said drain region comprises a third region and a fourth region, both being of said first conductivity type, said fourth region being formed between the channel forming region and said third region, and wherein said semiconductor region of said second conductivity type includes a deeper formed region of said second conductivity type extending to a depth beneath said third and fourth regions and on the channel forming side of said fourth region.

28. A semiconductor integrated circuit device according to claim 27, wherein said first and second regions are formed in self-alignment with said controlling and floating gates thereof, and wherein there is further included side wall spacers along opposing commonly extending side walls of said controlling and floating gates, such that said third region is formed in self-alignment with a corresponding side wall spacer and said controlling and floating gates, and said fourth region is formed in self-alignment with said controlling and floating gates.

29. A semiconductor integrated circuit device according to claim 26, wherein said EEPROM is flash type EEPROM.

30. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a memory cell which is constituted by a single field effect transistor, said memory cell comprising:

a control gate;

a floating gate positioned under said control gate;

a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;

a second gate insulation film formed between the two gates; and

source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of a first conductivity type, said channel forming region being a second conductivity type, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region and having a doping concentration lower than that of said first region, and the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region,

wherein said source region further includes a third region surrounding said first region, said third region has a doping concentration lower than that of said first region,

wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot carriers, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate,

wherein said memory cell erases the data, when a second predetermined potential is applied between said source region and said control gate, by emitting said injected carriers from said floating gate to said first region by tunneling through said first gate insulation film, and

wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third potential is lower in magnitude than said first predetermined potential and said first, second and third predetermined potentials have the same polarity.

31. A semiconductor integrated circuit device having an electrically erasable programmable read only memory (EEPROM) including a memory cell which is constituted by a single field effect transistor, said memory cell comprising:

a control gate;

a floating gate positioned under said control gate;

a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;

a second gate insulation film formed between the two gates;

source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates,

said source and drain regions being of a first conductivity type, said channel forming region being a second conductivity type, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region and having a doping concentration lower than that of said first region, and the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region; and

a semiconductor region of said second conductivity type formed in said semiconductor substrate, said semiconductor region being in contact with said second region on the channel region side thereof, and said semiconductor region having a doping concentration higher than that of said channel forming region,

wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot carriers, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate,

wherein said memory cell erases the data, when a second predetermined potential is applied between the source region and said control gate, by emitting said injected carriers from said floating gate to said first region by tunneling through said first gate insulation film, and

wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third potential is lower in magnitude than said first predetermined potential and said first, second and third predetermined potentials have the same polarity.

32. A semiconductor integrated circuit device according to claim 31, wherein said source region includes a third region surrounding said first region, said third region has a doping concentration lower than that of said first region.

33. An electrically erasable memory device including a plurality of memory cells each of which is constituted by a single field effect transistor, said memory cell comprising:

a control gate coupled to a word line;

a floating gate positioned under said control gate;

a first gate insulation film formed between a main surface of a semiconductor substrate and said floating gate;

a second gate insulation film formed between the two gates;

source and drain regions formed in said semiconductor substrate at said main surface and on opposite sides of a channel forming region positioned beneath the two gates, said source and drain regions being of n-type conductivity, said channel forming region being p-type conductivity, said source region including a first region extending under said floating gate, said drain region including a second region being formed as a substrate surface region adjacent said channel forming region, the junction depth of said first region into said semiconductor substrate, with respect to said main surface thereof, being greater than that of said second region; and

a semiconductor region of p-type conductivity type formed in said semiconductor substrate, said semiconductor region is in contact with said second region on the channel region side thereof,

wherein said memory cell stores data, when a first predetermined potential is applied to said drain region, by injecting hot electrons, which are generated in said semiconductor substrate in the vicinity of said second region, into said floating gate during a writing operation,

wherein said memory cell erases the data, when a second predetermined potential is applied between said first region and said control gate, by emitting said injected electrons from said floating gate to said first region by tunnelling through said first gate insulation film during an erasing operation;

wherein said first region has a doping concentration higher than that of said second region so as to reduce surface depletion of said first region at the time of said erasing operation,

wherein said semiconductor region has a doping concentration higher than that of said channel forming region so as to enhance the intensity of an electric field in the vicinity of said second region for increasing the generation of hot electrons at the time of said writing operation, and

wherein the data of said memory cell is read when a third predetermined potential is applied to said drain region, said third predetermined potential is lower in magnitude than said first predetermined potential.

34. A semiconductor integrated circuit device according to claim 33, wherein said first region is extended to partially underlie said floating gate and thereby effect an overlapped area between said first region and said floating gate.