Method for terminating harmonics of transistors

• US 5,300,895 A
• Filed: 10/01/1992
• Issued: 04/05/1994
• Est. Priority Date: 10/01/1992
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jones, Martin E.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/955,527
• Time in Patent Office: 551 Days
• Field of Search: 330/207 A, 330/251, 330/306, 333/175, 333/176
• US Class Current: 330/251
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence

Abstract

Generally, and in one form of the invention, a method is disclosed for terminating third harmonic frequency of a transistor amplifier comprising: determining the magnitude of the susceptance at the third harmonic frequency of initial circuitry, 41, 43, and 45, attached to the output of a transistor 39, wherein the initial circuitry has no third harmonic termination; determining whether the susceptance of the circuitry presented to the output of the transistor 39 is capacitive or inductive at the third harmonic frequency; and adding a compensating parallel susceptance 60 to the output of the transistor 39 that is substantially equal in magnitude to the susceptance of the circuitry attached to the output of the transistor 39, but capacitive if the susceptance of the circuitry presented to the output of the transistor 39 is inductive, or inductive if the susceptance presented to the output of the transistor 39 is capacitive, whereby the imaginary part of the susceptance of the total circuitry attached to the output of the transistor 39 is made small at the third harmonic frequency.

Claims

1. A method for terminating a third harmonic frequency of a transistor amplifier comprising:

determining the magnitude of the susceptance at said third harmonic frequency of initial circuitry attached to an output of a transistor, wherein said initial circuitry has no third harmonic termination;

determining whether the susceptance of said circuitry attached to the output of said transistor is capacitive or inductive at said third harmonic frequency; and

adding compensating parallel susceptance to the output of said transistor that is substantially equal in magnitude to the susceptance of said initial circuitry attached to the output of said transistor, but capacitive if said susceptance of said circuitry presented to the output of said transistor is inductive, or inductive if said susceptance presented to the output of said transistor is capacitive, whereby the imaginary part of the susceptance of the total circuitry attached to the output of said transistor is made small at said third harmonic frequency.

2. The method of claim 1 further comprising the step of forming said initial circuitry to include a fundamental-frequency matching circuit and a bias circuit.

3. The method of claim 2 wherein said step of adding compensating parallel susceptance to said output of said transistor comprises adding a shunt capacitance to said output of said transistor.

4. The method of claim 2 further comprising the step of forming said bias circuit to include a parallel-resonant network comprising an inductive element and a capacitive element, said resonant network being resonant at a fundamental frequency of said transistor-amplifier.

5. The method of claim 4 further comprising the step of adding the value of said compensating susceptance to said inductive element or said capacitive element of said bias circuit, and further wherein the inductance or capacitance of an element to which the compensating element is not added is adjusted so that said parallel resonant network is resonant at said fundamental frequency after said compensating susceptance is added to said inductive element or said capacitive element of said bias circuit.

6. The method of claim 2 further comprising the step of connecting a network for terminating a second harmonic frequency to said output of said transistor, said network comprising an inductive element in series with a capacitive element.

7. The method of claim 6 further comprising the step of adding the value of said compensating susceptance to said inductive element or said capacitive element of said network for terminating said second harmonic frequency, and further wherein the inductance or capacitance of an element to which the compensating element is not added is adjusted so that said network for terminating said second harmonic frequency is resonant at said second harmonic frequency.

8. The method of claim 1 further comprising the step of forming said transistor, wherein said transistor comprises a heterojunction.

9. A circuit for terminating a third harmonic frequency of a transistor amplifier comprising:

a matching circuit connected to an output of said transistor, said matching circuit having a first susceptance at said third harmonic frequency;

a bias circuit connected to said output of said transistor, said bias circuit having a second susceptance at said third harmonic frequency; and

a parallel compensating susceptance connected to an output of said transistor that is substantially equal in magnitude to the sum of said first susceptance and said second susceptance, but capacitive if said sum is inductive, or inductive if said sum is capacitive, whereby the imaginary part of the susceptance of the total circuitry attached to the output of said transistor is made small at said third harmonic frequency.

10. The circuit of claim 9 wherein said compensating susceptance is capacitive.

11. The circuit of claim 9 wherein said matching circuit comprises a series inductance and a shunt capacitance.

12. The circuit of claim 9 wherein said bias circuit comprises a parallel resonant network comprising an inductive element and a capacitive element, said resonant network being resonant at a fundamental frequency of said transistor.

13. The circuit of claim 9 further comprising a network for terminating a second harmonic frequency of said transistor amplifier.

14. The circuit of claim 9 wherein said transistor is a heterojunction bipolar transistor.

15. A circuit for terminating a third harmonic frequency of a transistor comprising:

a matching circuit connected to an output of said transistor, said matching circuit having a first susceptance at said third harmonic frequency;

a bias circuit connected to said output of said transistor, said bias circuit having a second susceptance at said third harmonic frequency, wherein the sum of said first susceptance and said second susceptance is small at said third harmonic frequency.

16. The circuit of claim 15 wherein said matching circuit comprises a series inductance and a shunt capacitance.

17. The circuit of claim 15 wherein said bias circuit comprises a parallel resonant network comprising an inductive element and a capacitive element, said resonant network being resonant at a fundamental frequency of said transistor.

18. The circuit of claim 15 wherein said transistor is a heterojunction bipolar transistor.

19. A circuit for terminating a third harmonic frequency of a transistor comprising:

a matching circuit connected to an output of said transistor, said matching circuit having a first susceptance at said third harmonic frequency;

a bias circuit connected to said output of said transistor, said bias circuit having a second susceptance at said third harmonic frequency; and

a network for terminating a second harmonic frequency of said transistor amplifier, said network having a third susceptance, and further wherein the sum of said first susceptance, said second susceptance, and said third susceptance is small at said third harmonic frequency.

20. The circuit of claim 19 wherein said matching circuit comprises a series inductance and a shunt capacitance.

21. The circuit of claim 19 wherein said bias circuit comprises a parallel resonant network comprising an inductive element and a capacitive element, said resonant network being resonant at a fundamental frequency of said transistor.

22. The circuit of claim 19 wherein said transistor is a heterojunction bipolar transistor.