Data slicing system

• US 5,301,023 A
• Filed: 04/07/1993
• Issued: 04/05/1994
• Est. Priority Date: 10/18/1991
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: Zenith Electronics Corporation (LG Corporation)
• Inventors: Zato, Thomas J.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Metjahic, Safet
• Application Number:
  US08/045,275
• Time in Patent Office: 363 Days
• Field of Search: 358/147, 358/146, 358/142, 358/13, 375/76, 375/22
• US Class Current: 348/476
• CPC Class Codes: H04N 7/0355 for discrimination of the binary level of the digital data, e.g. amplitude slicers

Abstract

A slice circuit for a data signal includes a clamp for clamping the data signal and a comparator having a first input coupled to the clamp, a second input coupled to a filter and an output coupled to a D/A converter. The output of the D/A converter is coupled to the filter such that a pulse width modulated signal is developed in the comparator output which is converted to a DC voltage by the D/A converter and filter for controlling the data slice level. The pulse width modulated signal is the sliced data.

Claims

1. A method of slicing a data signal comprising:

clamping the data signal to a reference level;

applying the clamped data signal to one input of a comparator to produce a sliced output;

sampling the sliced output of the comparator with a high frequency dot clock to produce a series of positive and negative logic levels;

applying the series of positive and negative logic levels to a D/A converter;

filtering the output of the D/A converter to develop a DC voltage; and

applying the DC voltage to the other input of said comparator to adjust the slice level of the comparator.

2. The method of claim 1 wherein said data signal is included in a television signal line and is preceded by a horizontal sync pulse, the tip of said horizontal sync pulse establishing said reference level.

3. A data slice circuit comprising:

clamp means for clamping a received data signal to a reference level;

a comparator having a first input coupled to said clamp means, a second input and an output;

means for sampling the output of said comparator with a high frequency dot clock to develop a series of positive and negative logic levels for a period of said data signal;

a D/A converter coupled to said comparator output and receiving said series of positive and negative logic levels; and

filter means coupled between the output of said D/A converter and said second input of said comparator for developing a DC voltage representative of said series of positive and negative logic levels and for applying said DC voltage to said second comparator input for adjusting the slice level of said comparator.

4. A method of optimizing the slice level of a digital data signal comprising a run-in portion and a data portion of the same data rate comprising:

clamping the digital data signal to a reference level;

applying the clamped data signal to one input of a comparator for slicing the clamped data signal at a first level;

sampling the sliced data signal with a high frequency dot clock to generate a series of positive and negative logic levels for a period of the sliced data signal;

applying said series of positive and negative logic levels to a D/A converter;

filtering the output of said D/A converter to develop a DC voltage based upon said series of positive and negative logic levels; and

applying the Dc voltage to another input of said comparator to adjust said first level.