Method of and apparatus for constructing a control system and control system created thereby

• US 5,301,100 A
• Filed: 04/29/1991
• Issued: 04/05/1994
• Est. Priority Date: 04/29/1991
• Status: Expired due to Fees

• Current Assignee: Janusz A. Dobrowolski
• Original Assignee: Janusz A. Dobrowolski
• Inventors: Wagner, Ferdinand H.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Garland, Steven R.
• Application Number:
  US07/693,936
• Time in Patent Office: 1,072 Days
• Field of Search: 364/148, 364/140, 364/141, 364/926.9-926.93, 364/949-949.2
• US Class Current: 700/19
• CPC Class Codes: G05B 19/0426 Programming the control sequence
• CPC Class Codes: G05B 2219/23289 State logic control, finite state, tasks, machine, fsm

Abstract

A method of and apparatus for constructing a control system and a control system created thereby which is based on a finite state machine with constant code (FSMcc). An input preprocessor module normalizes input signals as required by the FSMcc logical processing unit. An output postprocessor module changes the normalized finite state machine outputs to real signals required by the controlled process or apparatus. The input preprocessor allows for a different finite state machine required for an application to be executed by the same constant code contained in the FSMcc microcode storage. An application logic table for the FSMcc is constructed using a specific organization of data representing application logic conditions. This organization allows the entire application logic to be expressed in a table of a technically feasible size. The size of the FSMcc application logic table memory is greatly reduced. The symbolic application logic table is build in a simplified form using implied AND and OR logical operators. This symbolic application table is directly converted into the FSMcc application logic table.

Claims

1. A method of specifying a control system for a process or an apparatus to be controlled comprising:

a) identifying one or more detectable conditions associated with the controlled process or apparatus;

b) providing a separate input name for each detectable condition wherein the presence of the respective detectable condition is indicated by the respective name having an asserted value;

c) storing the input names;

d) identifying one or more control actions which can be taken to control the process or apparatus;

e) providing a separate output name for each identified control action;

f) storing the output names;

g) automatically producing an application logic table, wherein each input name is represented by a predetermined number of bit positions and combinations of input names are logically coupled together by implied AND and OR operators and wherein such combinations of input names are associated with output names;

h) storing the table; and

i) loading the application logic table into the control system.

2. The method of claim 1 wherein each logical combination of input names is selected and stored as an input word in the form of a pattern of bits.

3. A method of claim 2 wherein each input name is represented by at least one bit.

4. The method of claim 2 wherein at least one input word is selected and stored as a control word in the form of a pattern of bits.

5. A method of claim 4 wherein each input name is represented by at least one bit.

6. The method of claim 4 including linking input names by implied boolean AND operators to form at least one control word in the form of a pattern of bits.

7. The method of claim 6 including matching said pattern of bits in an input word with said pattern of bits in a control word to determine if the pattern of bits in said control word is a subset of the pattern of bits in said input word.

8. The method of claim 6 including linking groups of control words by the boolean OR operator.

9. The method of claim 1 wherein at least one of the detectable conditions corresponds to a measured input signal.

10. The method of claim 9 wherein said measurement of said input signal is in digital form.

11. The method of claim 9 wherein said measurement of said input signal is in analog form, further including converting said measurement to digital form before storing it.

12. The method of claim 1 including identifying a plurality of input conditions.

13. The method of claim 1 wherein at least one input name represents an unchanging parameter.

14. The method of claim 1 wherein a possible number of input signals and the number of input names are different from one another.

15. The method of claim 14 wherein the possible number of input signals is less than the number of input names.

16. The method of claim 14 wherein the possible number of input signals is greater than the number of input names.

17. The method of claim 1 wherein said output names are determined by said input names and a state of a finite state automata.

18. An apparatus for constructing a control system for a controlled process or controlled apparatus comprising:

a) input means for receiving

(1) a plurality of input names wherein each name corresponds to a detectable condition of said controlled process or apparatus, and

(2) output names corresponding to possible control actions which can be taken to control said controlled process or controlled apparatus,

b) memory means for storing said input names and said output names,

c) data processing means for using said stored input names and said stored output names to produce an application logic table associating combinations of input names with output names, and

d) output means for loading said application logic table into a control system.

19. The apparatus of claim 18 wherein said control system is a finite state machine with constant code.

20. The apparatus of claim 19 wherein said input means is adapted to receive data representing all transitions of said control system with combinations of input names, said memory means is adapted to store said data and said processing means uses said data to produce said application logic table.

21. The apparatus of claim 20 wherein said combinations of input names are determined by implied boolean logic operators.

22. The apparatus of claim 21 wherein said implied boolean operators consist of implied AND type operators and implied OR type operators.