Method for identifying a semiconductor die using an IC with programmable links
First Claim
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1. A method for identifying a semiconductor die comprising;
- forming a programmable integrated circuit on the die including programmable links connected to output nodes and to an FET transistor;
selectively activating the programmable links;
addressing the FET transistor with a predetermined address code to control current flow to each output node such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes; and
thenreading the predetermined identification code at the output nodes to identify the semiconductor die.
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Abstract
A method for identifying a semiconductor die includes a programmable integrated circuit formed on the semiconductor die. The programmable circuit includes FET transistors connected to output nodes and to programmable links such as fuses, anti-fuses or laser programmable links which are connected to ground. A gate element of each transistor is connected to an address line which controls current flow through the transistors to the output nodes. During manufacture, the programmable links can be selectively activated to create an identification code which can be read at the output nodes of the integrated circuit upon input of a predetermined address code.
171 Citations
19 Claims
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1. A method for identifying a semiconductor die comprising;
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forming a programmable integrated circuit on the die including programmable links connected to output nodes and to an FET transistor; selectively activating the programmable links; addressing the FET transistor with a predetermined address code to control current flow to each output node such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes; and
thenreading the predetermined identification code at the output nodes to identify the semiconductor die. - View Dependent Claims (2, 3, 4)
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5. A method for identifying a semiconductor die comprising:
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forming a programmable integrated circuit on the semiconductor die including at least two output nodes with each output node connected to a programmable link and to an FET transistor and with each transistor having a gate element addressable with a predetermined address input to control a current flow to the output nodes; selectively activating the programmable links of the integrated circuit; addressing the gate elements of the transistors with a predetermined address code such that for a given address code and based on a condition of the programmable links a predeterminal identification code can be read at the output nodes; and reading an output signal at the output nodes representative of the identification code. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
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14. A programmable integrated circuit for identifying a semiconductor die, said circuit formed on the die and comprising:
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first and second pairs of FET transistors, each pair of FET transistors connected to an output node of a conductive line having multiple output nodes; an address line connected to a gate element of each transistor for controlling current flow through each pair of FET transistors to the output nodes; and first and second programmable links connected to the first and second pairs of transistors respectively and to ground with the programmable links adapted to be selectively activated to create an identification code readable at the output nodes upon input of a predetermined address code to the address lines such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes to identify the die. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification