Anti-fuse circuit and method wherein the read operation and programming operation are reversed

• US 5,301,159 A
• Filed: 02/05/1993
• Issued: 04/05/1994
• Est. Priority Date: 02/05/1993
• Status: Expired

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Roger R.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/013,896
• Time in Patent Office: 424 Days
• Field of Search: 365/96, 365/225.7, 257/50, 257/530
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current is flowing in the second direction during a normal circuit operation, such as a read operation, wherein the first and second directions are opposite of one another. Thus the invention facilitates the use of a low programming potential while minimizing leakage current.

Claims

1. A semiconductor memory device having a circuit for minimizing leakage current comprising an anti-fuse element wherein the anti-fuse element is biased for a current to flow in a first direction or the current is flowing in said first direction during a first operation of the memory circuit, and said anti-fuse element is biased for current to flow in a second direction or the current flows in said second direction during a second operation of the memory circuit, said first and second directions being opposite of one another.

2. The memory device as specified in claim 1, wherein said first operation is a programmable operation, and wherein said second operation is a read operation.

3. The memory device as specified in claim 1, wherein a resistance of said anti-fuse element is reduced when the current initially flows through the anti-fuse element.

4. A memory device, comprising:

a) a serial device, having a first terminal and a second terminal;

b) a first conductive plate in electrical communication with said first terminal of said serial device;

c) a second conductive plate;

d) a dielectric layer interposed between said first and said second conductive plates, said dielectric layer capable of electrically isolating said first and second conductive plates one from the other; and

e) a control means for connecting a first and second potential bias across said second terminal of said serial device and said second conductive plate, said first potential bias capable of effecting a reduction in a resistance of said dielectric layer, said reduction in said resistance providing an electrical connection between said first and second conductive plates, said first and second biases being opposite of one another such that a current would flow in a first direction in response to said first potential bias and the current would flow in a second direction in response to said second potential bias, said first and second directions being opposite of one another.

5. The memory device as specified in claim 4, wherein said first potential bias is capable of producing a breakdown current flowing in said first direction, said breakdown current breaking down said dielectric layer thereby effecting said reduction in said resistance of said dielectric layer.

6. A programmable memory circuit, comprising:

a) a control device having a first terminal and a second terminal;

b) an anti-fuse element having a first conductive plate and a second conductive plate and a dielectric layer, said dielectric layer electrically interposed between and capable of electrically isolating said first and second conductive plates one from the other, said first conductive plate of said anti-fuse element in electrical communication with the first terminal of said control device;

c) a first electrical configuration wherein said second terminal of said control device is connectable to a first potential source and said second conductive plate is connectable to a second potential source; and

d) a second electrical configuration wherein said second terminal of said control device is connectable to a third potential source and said second conductive plate is connectable to a fourth potential source.

7. The programmable memory circuit as specified in claim 6, wherein said control device and said anti-fuse element form a serial circuit, and wherein when said serial circuit is connected in said first electrical configuration said serial circuit is biased for a current to flow in a first direction or the current is flowing in said first direction, and wherein when said serial circuit is connected in said second electrical configuration said serial circuit is biased for the current to flow in a second direction or the current is flowing in said second direction, said first and second directions being opposite of one another.

8. The programmable memory circuit as specified in claim 6, wherein said first potential source and said fourth potential source provide substantially equivalent potential values.

9. The programmable memory circuit as specified in claim 6, wherein said third potential source and said second potential source provide substantially equivalent potential values.

10. The programmable memory circuit as specified in claim 6, wherein the circuit is configured according to said first electrical configuration for a normal operation of the programmable memory circuit and wherein the circuit is configured according to said second electrical configuration for a programming operation of the programmable memory circuit.

11. A circuit for programming a programmable node, comprising:

a) a programmable device having first and second conductive terminals interposed by a programmable layer, said programmable device in electrical communication with and interposed between the programmable node and a first node, said first node alternately connectable to a first potential and a second potential;

b) a series device in electrical communication with and interposed between said programmable node and a second node, said second node alternately connectable to a third and a fourth potential; and

c) the programmable node capable of having a first programmable potential when said programmable layer electrically isolates said first and second conductive terminals, the programmable node capable of having a second programmable potential subsequent to a breakdown of said programmable layer by a programmable current flow in a first direction resulting from said first and third potentials at said first and second nodes respectively, a value of said first and second programmable potentials of said programmable node available when said first and second nodes are electrically connected to second and fourth potentials respectively.

12. The circuit as specified in claim 11, wherein said second and fourth potentials on said first and second nodes provides a bias potential between said first and second node which could cause current to flow in a second direction, said first and second directions being opposite one to the other.

13. A method of operating a memory device having a plurality of programmable nodes, each one of said plurality in electrical communication with a respective one of a plurality of first conductive plates, each first conductive plate having a corresponding second conductive plate, comprising:

a) determining which of said programmable nodes of said plurality are selected and which are non-selected;

b) electrically insulating said first conductive plate from said corresponding second conductive plate for said first conductive plates in electrical communication with non-selected said programmable nodes;

c) applying a first potential bias across said first and said corresponding second conductive plates for said first conductive plates in electrical communication with selected said programmable nodes;

d) providing, in response to said step of applying said first potential bias, electrical communication between said first and said second corresponding conductive plates for said first conductive plates in electrical communication with selected said programmable nodes; and

e) applying a second potential bias across a circuit having an addressed one of said programmable nodes of said plurality in order to perform a circuit function, said first potential bias and said second potential bias having opposite polarities such that electrical current would flow or current flows in opposite directions in response to said first potential bias and in response to said second potential bias.

14. The method as specified in claim 13, further comprising breaking down said dielectric layer interposed between said first and second conductive plates due to an electrical current flowing between said first and second conductive plates, said current flow generated in response to said step of applying said first potential bias.

15. A method of operating a programmable memory device having an anti-fuse element, comprising:

a) applying a first potential wherein the anti-fuse element is biased for a first current to flow in a first direction or the first current is flowing in said first direction during a first operation of said programmable memory device; and

b) applying a second potential bias wherein said anti-fuse element is biased for a second current to flow in a second direction or the second current flows in said second direction during a second operation of said programmable memory device, said first and second directions being opposite of one another.

16. A method for programming a node in electrical communication with an anti-fuse device, comprising:

a) substantially prohibiting current flow between a first conductive surface and a second conductive surface of said anti-fuse device when said node is non-selected;

b) electrically connecting said node to said second conductive surface when said node is selected, said electrically connecting performed in response to a first current flow, having a first direction, between said first and second conductive surfaces; and

c) providing a bias across a circuit containing said node and said anti-fuse device, such that a second current would flow in a second direction or the second current flows in said second direction between said first and said second conductive surfaces, said first and second directions being opposite of one another.

17. The method as specified in claim 16, wherein said step of providing is performed for a read operation.

18. On a monolithic integrated circuit device, a sub-circuit for minimizing leakage current comprising an anti-fuse element wherein the anti-fuse element is biased for a current to flow in a first direction or the current is flowing in said first direction during a first operation of the sub-circuit, and said anti-fuse element is biased for current to flow in a second direction or the current flows in said second direction during a second operation of the sub-circuit, said first and second directions being opposite of

19. The sub-circuit as specified in claim 18, wherein said first operation is a programmable operation, and wherein said second operation is a read operation.

20. The sub-circuit as specified in claim 18, wherein a resistance of said anti-fuse element is reduced when the current initially flows through the anti-fuse element.