Half-speed clock recovery and demultiplexer circuit

• US 5,301,196 A
• Filed: 03/16/1992
• Issued: 04/05/1994
• Est. Priority Date: 03/16/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ewen, John F., Widmer, Albert X.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Patel, Ajit
• Application Number:
  US07/853,215
• Time in Patent Office: 750 Days
• Field of Search: 370/77, 370/105.3, 370/105.2, 370/112, 370/84, 375/119, 375/120, 307/243, 307/244, 328/153, 328/154
• US Class Current: 370/518
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.

Claims

1. A clock recovery and demultiplexer circuit for recovering a clock signal from a received data signal and for demultiplexing the received data signal, and operating at a fraction of the data rate of the received data signal, said circuit comprising:

a. clock signal generating means for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal;

b. comparing means for comparing the phase angle between said generated reference clock signal and the received data signal;

c. frequency adjusting means responsive to said phase angle comparing means for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data signal; and

d. demultiplexing means for demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.

2. The clock recovery and demultiplexer circuit of claim 1, wherein:

a. said clock signal generating means comprises means for generating 0-degree and 90-degree reference clock signals at one half the data rate of the received data signal;

b. said comparing means comprises a phase comparator circuit for comparing the phase angle between said generated reference clock signal and the received data signal; and

c. said demultiplexing means comprises means for demultiplexing the received data signal into two separate data streams, both at half the clock rate of the received data signal.

3. The clock recovery and demultiplexer circuit of claim 2, wherein:

said means for generating a 0-degree and 90-degree reference clock signal is a ring oscillator;

said half-speed phase comparator circuit comprises two edge-triggered flip-flops and an exclusive OR-gate; and

said demultiplexing means comprises two edge-triggered flip-flops.

4. The clock recovery and demultiplexer circuit of claim 3, further comprising an inverter for inverting the received data signal, and an inverter for inverting said 90-degree clock signal.

5. The clock recovery and demultiplexer circuit of claim 1, wherein:

a. said clock signal generating means comprises means for generating 0-degree, 45-degree, 90-degree and 135-degree reference clock signals at one quarter the data rate of the received data signal;

b. said comparing means comprises phase comparator circuit for comparing the phase angle between the generated reference clock signal and the received data signal; and

c. said demultiplexing means comprises means for demultiplexing the received data signal into four separate data signals, each at one quarter the clock rate of the received data signal.

6. The clock recovery and demultiplexer circuit of claim 5, wherein:

said means for generating a reference clock signal is a ring oscillator;

said quarter speed phase comparator circuit comprises four edge-triggered flip-flops and a parity generator; and

said demultiplexing means comprises four flip-flops.

7. The quarter speed clock recovery and demultiplexer circuit of claim 6 further comprising an inverter for inverting the received data signal, and inverters for inverting the 45-and 135-degree clock signals.

8. A method of recovering a clock signal from a received data signal and for demultiplexing the received data signal, comprising the steps of:

a. generating a plurality of phases of a reference clock signal at a rate less than the data rate of the received data signal;

b. comparing the phase angle between said generated reference clock signal and the received data stream;

c. adjusting the frequency of said generated reference clock signal as a function of said comparing step to thereby synchronize said generated reference clock signal and the received data signal; and

d. demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal, using at lease one each of the phases of the generated reference clock signal and inverted phases of the generated reference clock signal.

9. The method of claim 8 further comprising the steps of:

generating a 0-degree and a 90-degree reference clock signal at one half the data rate of the received data signal; and

demultiplexing the received data signal into two separate data signals both at one half the clock rate of the received data signal.

10. The method of claim 8 further comprising the steps of:

generating a 0-degree, 45-degree and 90-degree an 135-degree clock signal; and

demultiplexing the received data signal into four separate signals each at one quarter the clock rate of the received data signal.

11. A clock recovery and demultiplexer circuit for recovering clock signal from a received data signal and for demultiplexing the received data stream, and operating at a fraction of the data rate of the received data signal, said circuit comprising:

a. an oscillator for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal;

b. a phase comparator for comparing the phase angle between said generated reference clock signal and the received data signal;

c. a feedback loop for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data stream in response to a lead-lag signal generated by said phase comparator; and

a demultiplexer for demultiplexing the received data stream into parallel signals at data rates lower than the data rate of the received data stream using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.