Built-in self test circuit

• US 5,301,199 A
• Filed: 12/15/1992
• Issued: 04/05/1994
• Est. Priority Date: 12/16/1991
• Status: Expired due to Fees

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone Corporation
• Inventors: Ikenaga, Takeshi, Takahashi, Jun-ichi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US07/991,535
• Time in Patent Office: 476 Days
• Field of Search: 371/22.5, 371/25.1, 371/22.4, 371/22.1, 371/, 395/500
• US Class Current: 714/733
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 2201/83 the solution involving signatures

Abstract

A built-in self test circuit includes a pattern generator, a functional block subjected to a self test on the basis of an output from the pattern generator, a space compressor for compressing a test result of the functional block, and a comparator for comparing an output from the space compressor with an expected value and outputting a comparison result. The functional block has O (positive integer) inputs and M (positive integer) outputs. The pattern generator is constituted by a linear feedback shift register, having an output bit width P (P=O/N) which is 1/N of the inputs O of the functional block, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from the linear feedback shift register in units of N outputs and outputting, to the functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from the linear feedback shift register every P bits. The space compressor has a function of spatially compressing the M outputs from the functional block into L outputs (positive integer and M>L). The pattern generator, the functional block, the space compressor, and the comparator are built into a semiconductor chip into which other functional elements are built.

Claims

1. A built-in self test circuit comprising:

a pattern generator;

a functional block subjected to a self test on the bases of an output from said pattern generator;

a space compressor for compressing a test result of said functional block; and

a comparator for comparing an output from said space compressor with an expected value and outputting a comparison result,

wherein said functional block includes a plurality of modules having the same function and has a data input bit width O (positive integer) and a data output bit width M (positive integer),

said pattern generator is constituted by a linear feedback shift register, having an output bit width P which is an integer satisfied by the equation O/N<

=P <

O/(N+1) where N is an integer more than 2, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from said linear feedback shift register in units of N outputs and outputting, to said functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from said linear feedback shift register every P bits,

said space compressor has a function of spatially compressing the M outputs from said functional block into L outputs (positive integer and M>

L), and

said pattern generator, said functional block, said space compressor, and said comparator are built into a semiconductor chip into which other functional elements are built.

2. A circuit according to claim 1, wherein said functional block is constituted by modules arranged in line and having the same function.

3. A circuit according to claim 1, wherein said functional block is constituted by modules arranged in the form of an array and having the same function.

4. A circuit according to claim 2, wherein said functional block comprises a control unit for supplying a control signal to each of said modules.

5. A circuit according to claim 1, wherein said space compressor constitutes one stage.

6. A circuit according to claim 1, wherein said space compressor constitutes a plurality of stages which are constituted by different types of space compressing means.

7. A circuit according to claim 6, wherein said space compressor constitutes two stages, the first one of which is constituted by an exclusive OR type and the second one of which is constituted by multiple input linear feedback shift register.

8. A built-in self test circuit comprising:

a plurality of pattern generators; and

a plurality of functional blocks subjected to a self test on the basis of outputs from said pattern generators;

a plurality of space compressors for compressing test results of said functional blocks;

a time compressor for comparing an output from said time compressor with an expected value and outputting a comparison result,

wherein each of said functional blocks includes a plurality of modules having the same function and has a data input bit width O (positive integer) and a data output bit width M (positive integer),

each of said pattern generators is constituted by a linear feedback shift register, having an output bit width which is an integer satisfied by the equation O/N<

=P<

O/(N+1) where N is an integer more than 2, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing output from said linear feedback shift register in units of N outputs and outputting, to said functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from said linear feedback shift register every P bits,

each of said space compressors has a function of spatially compressing the M outputs from said functional block into L outputs (positive integer and M>

L),

said time compressor receives an output from each of said space compressors and supplying a time-compressed output to said comparator, and

said plurality of pattern generators, said plurality of functional blocks, said plurality of space compressors, said time compressor, and said comparator are built into a semiconductor chip into which other functional elements are built.

9. A circuit according to claim 8, further comprising selecting means, arranged between said space compressors and said time compressor, for selecting outputs from said space compressors.

10. A built-in self test circuit comprising:

a pattern generator; and

a functional block subjected to a self test on the bases of an output from said pattern generator,

wherein said functional block includes a plurality of modules having the same function and has a data input bit width O (positive integer) and a data output bit width M (positive integer),

said pattern generator is constituted by a linear feedback shift register, having an output bit width P which is an integer satisfied by the equation O/N<

=P <

O/(N+1) where N is an integer more than 2, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from said linear feedback shaft register in units of N outputs and outputting, to said functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from said linear feedback shift register every P bits,

a test result is checked on the basis of an output from said functional block, and

said pattern generator and said functional block are built into a semiconductor chip into which other functional elements are built.