Flexible dynamic memory controller

• US 5,301,278 A
• Filed: 04/23/1992
• Issued: 04/05/1994
• Est. Priority Date: 04/29/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Larky, Steven P., Sidoli, Paolo G., Bowater, Ronald J., St. Clair, Joe C.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Shin, C.
• Application Number:
  US07/873,880
• Time in Patent Office: 712 Days
• Field of Search: 395/275, 395/425, 360/233 X
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.

Claims

1. A method of operating a data processing system that includes at lest two devices capable of sourcing different types of memory access requests to a plurality of memory banks, wherein at least one of the memory banks is capable of having an access characteristic that differs from an access characteristic of others of the memory banks, the method including a step of operating a memory controller that is responsive to said memory access requests for providing control signals to said memory banks for controlling sequences of operation of said memory banks, the step of operating a memory controller including the steps of:

storing information within the memory controller that (a) specifies first memory access characteristics for each of the plurality of memory banks, the first memory access characteristics for each of the plurality of memory banks being related to an operating speed of the memory bank, and (b) that specifies a second memory access characteristic for each of the plurality of memory banks, the second memory access characteristic for each memory bank being related to an identification of a device that sources a memory access request to the memory bank;

decoding a memory access request within the memory controller to identify which one of the plurality of memory banks is to be addressed, and to identify the device that is sourcing the memory access request; and

providing the control signals from the memory controller to the identified memory bank to determine a duration of a cycle time of the control signals, at a time when the control signals are provided to the identified memory bank, in accordance with the stored information for the identified memory bank and in accordance with the identification of the device that is sourcing the memory access request.

2. A method of operating a data processing system that includes at least two devices capable of sourcing memory access requests with different timings to a plurality of memory banks, wherein at least one of the memory banks is capable of having an access characteristic that differs from an access characteristic of others of the memory banks, the method including a step of operating a memory controller that is responsive to said memory access requests for providing control signals to said memory banks for controlling sequences of operation of said memory banks, the step of operating a memory controller including the steps of:

storing, within the memory controller, information that specifies memory access characteristics for each of the plurality of memory banks, the memory access characteristics for each of the plurality of memory banks including a RAS precharge time associated with a row address strobe (RAS) signal that is provided to the memory bank and a CAS precharge time associated with a column address strobe (CAS) signal that is provided to the memory bank;

decoding a memory access request that is received from one of the at least two devices, the memory access request begin decoded within the memory controller to determine an identification of a memory bank that is selected by the memory access request and to determine a row address and a column address of the selected memory bank;

providing the control signals, including the row address strobe (RAS) signal and the column address strobe (CAS) signal, from the memory controller to the selected memory bank for controlling a sequence of operation of the selected memory bank; and

wherein the step of providing includes a step of

determining, during a time that the RAS signal and the CAS signal are provided to the selected memory bank, a RAS precharge time associated with the RAS signal and a CAS precharge time associated with the CAS signal in accordance with the stored information for the selected memory bank.

3. The method of claim 2, wherein the step of storing further stores, for each of the plurality of memory banks, a maximum time that the RAS signal is active, and wherein the step of providing further includes the steps of:

counting with the memory controller, beginning at a time that the RAS signal is provided to the selected memory bank, a predetermined number of clock signals, the clock signals occurring at periodic intervals; and

removing, with the memory controller, the RAS signal from the selected memory bank when a predetermined number of clock signals have been counted, the predetermined number corresponding to the stored maximum time that RAS is active for the selected memory bank.

4. The method of claim 2, wherein a memory access request includes a plurality of bits for specifying a memory address, and wherein the step of providing further includes a step of:

comparing predetermined ones of the plurality of bits to other predetermined ones of a plurality of bits to determine if the memory access request is a page mode type of memory access request, the other predetermined ones of the plurality of bits being a plurality of bits that are stored within the memory controller in response to a prior memory access request.

5. The method of claim 2, wherein a memory access request includes a plurality of bits for specifying a memory address, wherein the memory controller includes means for storing the bits specifying a memory address from a prior memory access request, and further including a step of:

comparing a stored memory address from the prior memory access request to a memory address associated with a current memory access request to determine if the current memory access request is directed to a same memory page as the prior memory access request and, if so, performing the current memory access request in accordance with a page-mode memory cycle operation.

6. The method of claim 2, wherein the step of storing information that specifies memory access characteristics for each of the plurality of memory banks includes storing information specifying a RAS signal access time and a CAS signal access time for each of the plurality of memory banks, and wherein the step of providing further includes a step of:

determining a memory bank RAS signal access time and a memory bank CAS signal access time in accordance with an identification of the memory bank and in accordance with the stored information.

7. A method of operating a data processing system that includes at least two devices capable of sourcing memory access requests with different timings to a plurality of memory banks, wherein at least one of the memory banks is capable of having an access characteristic that differs from an access characteristic of others of the memory banks, the method including a step of operating a memory controller means that is responsive to said memory access requests for providing control signals to said plurality of memory banks for controlling sequences of operation of said plurality of memory banks, the step of operating a memory controller means including the steps of:

storing, within the memory controller means, information that specifies memory access characteristics for each of the plurality of memory banks, the memory access characteristics for each of the plurality of memory banks including a CAS signal access time, a CAS signal precharge time, a RAS signal access time, and a RAS signal precharge time for the memory bank;

decoding, within the memory controller means, a memory access request made by one of the processors to determine from the memory access request an identification of a memory bank specified by the memory access request and to determine a row address and a column address of the specified one of the memory banks;

accessing the specified one of the memory banks, the step of accessing the specified one of the memory banks including the steps of

activating a row address strobe (RAS) signal from the memory controller means in conjunction with providing the determined row address from the memory controller means to the specified one of the memory banks;

activating a column address strobe (CAS) signal from the memory controller means in conjunction with providing the determined column address from the memory controller means to the specified one of the memory banks; and

, while the RAS signal and the CAS signal are both activated, and before deactivating the RAS signal after a RAS signal access time has expired and before deactivating the CAS signal after a CAS signal access time has expired,

determining, within the memory controller means and in accordance with the stored information, if additional CAS signal access time is required and, if it is so determined, providing additional CAS signal access time to the specified one of the memory banks by maintaining the CAS signal asserted for a period of time equal to an additional CAS signal access time that is specified by the stored information;

determining, within the memory controller means and in accordance with the stored information, if additional CAS signal precharge time is required and, if it is so determined, providing additional CAS signal precharge time to the selected memory bank by deactivating the CAS signal while maintaining the RAS signal active for a period of time equal to an additional CAS signal precharge time that is specified by the stored information;

deactivating the RAS signal with the memory controller means; and

determining, within the memory controller means and in accordance with the stored information, if additional RAS signal precharge time is required, and, if it is so determined, providing additional RAS signal precharge time to the selected memory bank by maintaining the RAS signal deactivated for a period of time equal to an additional RAS signal precharge time that is specified by the stored information.

8. The method of claim 7 wherein the stored memory access characteristics for each memory bank also include an indication if each memory bank for which memory access characteristics are stored is an interleaved memory bank, and wherein the step of decoding includes a step of:

determining within the memory controller means, in accordance with the stored information, if the specified one of the memory banks is indicated to be an interleaved memory bank and, if the specified one of the memory banks is indicated to be an interleaved memory bank, the method further includes a step of enabling a bank address for a non-specified one of the interleaved memory banks and also enabling a bank address for the specified one of the memory banks;

otherwise if the specified one of the memory banks is indicated not to be an interleaved memory bank, the step of decoding includes a step of enabling only a bank address for the specified one of the memory banks.

9. The method of claim 7 wherein the step of storing further stores, for each of the plurality of memory banks, a maximum time that the RAS signal is active, and wherein the step of activating the RAS signal includes the steps of:

counting with the memory controller means, beginning at the time that the RAS signal is activated, a predetermined number of clock signals; and

removing, with the memory controller means, the RAS signal from the specified one of the memory banks when a predetermined number of clock signals have been counted, the predetermined number corresponding to the stored maximum time that RAS is active for the specified one of the memory banks.

10. The method of claim 7 wherein, if it is determined that additional CAS signal precharge time is required, there is performed an additional step of deactivating the CAS signal while maintaining the RAS signal activated.

11. The method of claim 7 wherein a memory access request includes a plurality of bits for specifying a memory address, and wherein the method includes the steps of:

storing, within the memory controller means, the plurality of bits that specify a memory address for a memory access request;

wherein the step of deactivating the RAS signal includes a preliminary step of comparing a stored memory address to a memory address associated with a current memory access request made by one of the processors to determine if the current memory access request requests access to a same page of a memory as a prior memory access request having a stored memory address and, if it is determined that the current memory access is to the same memory page as a prior memory access having the stored address, the step of deactivating the RAS signal includes additional preliminary steps of maintaining the RAS signal activated, deactivating the CAS signal;

providing a new column address; and

reactivating the CAS signal to accomplish a page-mode type of memory access.

12. In a data processing system including at least two devices capable of sourcing memory access requests with different timings to a plurality of memory banks, wherein at least one of the memory banks is capable of having an access characteristic that differs from an access characteristic of others of the memory banks, memory controller means responsive to memory access requests for providing control signals to the plurality of memory banks for controlling sequences of operation of the plurality of memory banks, the memory controller means comprising:

means for decoding a memory access request for identifying which one of the plurality of memory banks is to be addressed;

means for storing information that specifies first memory access characteristics for each of the plurality of memory banks, the first memory access characteristics for each of the plurality of memory banks being related to an operating speed of a memory bank for which the information is stored, the storing means further storing information that specifies a second memory access characteristic for each of the plurality of memory banks, the second memory access characteristic for each of the plurality of memory banks being related to an identification of a device that sources a memory access request to the memory bank; and

means, having an input coupled to an output of the decoding means and an input coupled to an output of the storing means, for providing control signals from the memory controller means to the identified memory bank, the providing means including means for determining a duration of a cycle time of the control signals, during a time when the control signals are provided to the identified memory bank, in accordance with the information stored within the storing means for the identified memory bank and also in accordance with an identification of the device that sourced the memory access request to the identified memory bank.

13. In a data processing system including means for sourcing memory access requests to a plurality of memory banks, wherein at least one of the memory banks is capable of having an operating cycle time that differs from an operating cycle time of others of the memory banks, memory controller means responsive to memory access requests for providing control signals to the plurality of memory banks for controlling sequences of operation of the plurality of memory banks, the memory controller means comprising:

means for decoding a memory access request to determine an identification of a memory bank that is selected by the memory access request to be addressed, said decoding means further determining a row address and a column address of the selected memory bank to be addressed;

means for storing information that specifies memory access characteristics for each of the plurality of memory banks, the memory access characteristics for each of the plurality of memory banks including a row address strobe (RAS) precharge time and a column access strobe (CAS) precharge time of a memory bank for which the information is stored;

means, having an input coupled to an output of the decoding means and an input coupled to an output of the storing means, for providing the control signals, including a RAS signal and a CAS signal, to the selected memory bank for controlling a sequence of operation of the selected memory bank;

the means for providing including

means for determining, during a time that the RAS signal and the CAS signal are provided, a duration of the RAS precharge time associated with the RAS signal and a duration of the CAS precharge time associated with the CAS signal, said determining means making the determination in accordance with the information stored within the storing means for the selected memory bank.

14. A memory controller means as set forth in claim 13 wherein the storing means further stores, for each of the plurality of memory banks, a maximum time that the RAS signal is active, and wherein the providing means further includes means for counting a predetermined number of clock signals, beginning at the time that the RAS signal is provided to the selected memory bank, the clock signals occurring at predetermined intervals;

and means for removing the RAS signal from the selected memory bank when a predetermined number of clock signal shave been counted, the predetermined number corresponding tot he stored maximum time that the RAS signal is active for the selected memory bank.

15. A memory controller means as set forth in claim 13 wherein a memory access request includes a plurality of bits for specifying a memory address, and wherein the providing means further includes means for comparing predetermined ones of the plurality of bits to other predetermined ones of a plurality of bits to determine if the memory access request is a page-mode type of memory access request, the other predetermined ones of the plurality of bits being a plurality of bits associated with a prior memory access request, wherein said other predetermined plurality of bits are stored within storage means within said memory controller means.

16. A memory controller means as set forth in claim 13 wherein a memory access request includes a plurality of bits for specifying a memory address, wherein memory controller includes means for storing the bits specifying a memory address from a prior memory access request, and wherein the providing means further includes means for comparing a stored memory address from the prior memory access request to a memory address associated with a current memory access request to determine if the current memory access request is directed to a same memory page as the prior memory access request and, if so, for processing the current memory access request as a page-mode memory operation.

17. A memory controller means as set forth in claim 13 wherein the memory access characteristics for each of the plurality of memory banks also include a RAS signal access time and a CAS signal access time, and wherein the providing means further includes means for determining a memory bank RAS signal access time and a memory bank CAS signal access time in accordance with an identification of the memory bank being accessed.

18. Memory controller means for use in a data processing system of the type that includes data processing means for sourcing memory access requests to a plurality of memory banks, wherein at least one of the memory banks is capable of having an operating cycle time that differs from an operating cycle time of others of the memory banks, the memory controller means being responsive to the memory access requests for providing control signals to the plurality of memory banks for controlling sequences of operation of the plurality of memory banks, the memory controller means comprising:

means for decoding a memory access request made by the data processing means for selecting one of the plurality of memory banks to be addressed, said decoding means further determining a row address and a column address of the selected one of the memory banks;

means for storing information that specifies first memory access characteristics for each of the plurality of memory banks, the first memory access characteristics for each of the plurality of memory banks including a CAS signal access time, a CAS signal precharge time, a RAS signal access time, and a RAS signal precharge time of a memory bank for which the information is stored, the storing means further storing information that specifies a second memory access characteristic, including a CAS delay time, for each of the plurality of memory banks, the second memory access characteristic for each of the plurality of memory banks being related to an operating characteristic f the data processing means that sources a memory access request to the memory bank; and

means for accessing the selected memory bank, the accessing means comprising,

means for providing the determined row address and for activating a row address strobe (RAS) signal, for a RAS signal access time, in conjunction with providing the determined row address;

means for providing the determined column address and for activating a column address strobe (CAS) signal, for a CAS signal access time, in conjunction with providing the determined column address; and

memory bank access cycle control means, including,

first means, having input coupled to an output of the decoding means and an input coupled to an output of the storing means, and responsive to the RAS signal and the CAS signal being activated, for determining, in accordance with the stored information for the selected memory bank, if additional CAS signal access time is required and if additional CAS signal precharge time is required, and, if so, for providing additional CAS signal access time and additional CAS signal precharge time to the selected memory bank;

means for deactivating the RAS signal; and

second means, having an input coupled to an output of the decoding means and an input coupled to an output of the storing means, and responsive to the RAS signal being deactivated, for determining, in accordance with the stored information for the selected memory bank, if additional RAS signal precharge time is required, and, if so, providing additional RAS signal precharge time to the selected memory bank.

19. Memory control means as set forth in claim 18 wherein the stored first memory access characteristics for each of the plurality of memory banks also include an indication if the memory bank for which the information is stored is an interleaved memory bank, and wherein the memory bank access cycle control means further includes means, if the selected memory bank is determined to be an interleaved memory bank, for enabling a bank address to be applied to the selected memory bank and also to a non-selected memory bank.

20. Memory control means as set forth in claim 18 wherein the storing means further stores, for each of the plurality of memory banks, a maximum time that the RAS signal is active, and wherein the RAS signal activating means further includes means for counting a predetermined number of clock signals, beginning at the time that the RAS signal is activated for the selected memory bank;

and means for deactivating the RAS signal to the selected memory bank when a predetermined number of clock signals have been counted, the predetermined number corresponding to the stored maximum time that the RAS signal is active for the selected memory bank.

21. Memory control means as set forth in claim 18 wherein the first determining means further includes means, responsive to a determination that additional CAS signal precharge time is required for the selected memory bank, for deactivating the CAS signal, and wherein the second determining means is responsive to the deactivation of the CAS signal, when the first determining means determines that additional CAS signal precharge time is required for the selected memory bank, for maintaining the RAS signal activated for a predetermined interval of time.

22. Memory control means as set forth in claim 18 wherein a memory access request includes a plurality of bits for specifying a memory address, wherein the memory control means includes means for storing the bits specifying a memory address from a prior memory access request, and wherein the memory control means further includes means for comparing a stored memory address to a memory address associated with a current memory access request to determine if the prior memory access request requested access to a same page of memory as the current memory access request, and wherein the first determining means further includes means, responsive to a determination that the current memory access request is to a same memory page as the prior memory access request, for deactivating the CAS signal to the selected memory bank;

for providing a new column address to the selected memory bank; and

for reactivating the CAS signal to the selected memory bank to accomplish a page-mode type of memory access.

23. Memory control means as set forth in claim 18 wherein the memory cycle access control means includes state machine means having input signals coupled to an output of the storing means for generating the memory access control signals, for each of the plurality of memory banks, in accordance with the stored information.