Mixed-resolution, N-dimensional object space method and apparatus

• US 5,301,284 A
• Filed: 01/16/1991
• Issued: 04/05/1994
• Est. Priority Date: 01/16/1991
• Status: Expired due to Term

• Current Assignee: Walker-Estes Corporation
• Original Assignee: Walker-Estes Corporation
• Inventors: Estes, Mark D., Walker, John P.
• Primary Examiner(s): Bayerl, Raymond J.
• Application Number:
  US07/642,508
• Time in Patent Office: 1,175 Days
• Field of Search: 395/120, 395/161, 395/131, 395/155, 395/425, 395/62, 395/60, 395/10, 395/76, 395/400
• US Class Current: 711/203
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects
• CPC Class Codes: Y10S 715/966 Computer process, e.g. operation of computer

Abstract

Object spaces which mechanize higher order relationships between attributes which describe a particular problem domain. An abstract object description defined by a set of attributes and their corresponding values is transformed into a mixed-resolution, N-dimensional object space. The mixed-resolution, N-dimensional object space represents a mechanized, logically encoded expression of attribute relationships that can be visualized. The method and apparatus interleave the frame to generate an object descriptor and generate from the frame and the object descriptor, encoded names of spatial locations for each of the N dimensions of the mixed-resolution, N-dimensional, object space, conforming to a primary form of a reflected binary code. A virtual image of the N-dimensional, object space is generated from the dimensional-spatial locations and resolution-spatial locations, and attribute values corresponding to a region of the virtual image may be selected for display.

Claims

1. A process for dynamically configuring a logical architecture for using a digital-computing device and for controlling fundamental operations to transform said digital-computing device from a fixed-radix mode of operation imposed by physical architecture of said digital-computing device to a mixed-radix mode of operation, comprising the steps, using said digital-computing device, of:

a. encoding with said digital-computing device a logical name for each attribute describing a problem space to form an object frame for organizing a contiguous sequence of coded attribute names, each object frame having a logical one bit representing a dimension of an N-dimensional, object space and having a logical zero bit representing a degree of resolution for a range of possible values for a particular attribute for a dimension of an N-dimensional, object space;

b. interleaving bits of said object frame to generate an object descriptor, said object descriptor representing a name format for referencing storage locations of said digital-computing device and for controlling an order of the storage locations, the storage locations configured as spatial locations of said N-dimensional, object space;

c. configuring, from said object frame and said object description, the spatial locations as dimensional-spatial locations of said N-dimensional, object space;

d. configuring, from said object frame and said object descriptor, the spatial locations as resolution-spatial locations for a mixed-resolution, N-dimensional, object space; and

whereby, said mixed-radix mode of operating said computing device mechanizes methods of selecting mixed-radix expressions for elements, paths and relation of said mixed-resolution, N-dimensional, object space, without the steps of converting mixed-radix expressions to and from unit expressions imposed by the fixed-radix architecture of said computing device.

2. The process as set forth in claim 1 further including the step of repeating steps a though d in response to input to said computing device which changes the description of said problem space, wherein said steps configure a new logical architecture for a mixed-radix mode of operating said computing device.

3. The process as set forth in claim 1 or 2 wherein a machine process dynamically determines a problem space described by at least one attribute defining at least one dimension having at least one level of resolution for configuring storage locations of a digital computing device as spatial locations for a mixed-resolution, N-dimensional, object space.

4. The process as set forth in claim 1 or 2 wherein a user interactively determines a problem space described by at least one attribute defining at least one dimension having at least one level of resolution for configuring storage locations of a digital computing device having a display device for visualizing said problem space description as spatial locations for a mixed-resolution, N-dimensional, object space.

5. The process as set forth in claim 1 or 2 wherein an object selector for referencing a spatial location in a memory configured as a named spatial location of said mixed-resolution, N-dimensional, object space is logically generated by interleaving bits of a particular instance of frame data for a mixed-radix mode of operating said computing device.

6. The process as set forth in claim 1 or 2 wherein a relation between spatial locations in a memory configured as named spatial locations of said mixed-resolution, N-dimensional, object space is logically generated by changing the sense of particular object selector bits for a mixed-radix mode of operating said computing device.

7. The process as set forth in claim 1 or 2 wherein a path comprising a plurality of spatial locations in a memory configured as named spatial locations of said mixed-resolution, N-dimensional, object space is logically generated by changing the sense of particular object selector bits in a particular sequence for a mixed-radix mode of operating said computing device.

8. The process as set forth in claim 1 or 2 wherein a region comprising a plurality of spatial locations in a memory configured as named spatial locations of said mixed-resolution, N-dimensional, object space is logically generated by suppressing particular object selector bits for a mixed-radix mode of operating said computing device.

9. The process as set forth in claim 1 or 2 wherein multiple paths for concurrently selected paths comprising a plurality of spatial locations in a memory configured as named spatial locations of said mixed-resolution, N-dimensional, object space are logically generated by changing the sense of a plurality of object selector bits in a particular sequence for a mixed-radix mode of operating said computing device.

10. An object description system for controlling the logical manipulation of data storage locations of a memory of a digital-computing device configured as at least one mixed-resolution, N-dimensional, object space, wherein the object description system is described as a special purpose computing device having a mixed-radix logical architecture, said digital computing device including processor means for accessing said data storage locations;

signal communication means, operatively coupled to said processor means, for communicating control signals, address signals, and data signals to and from said processor means;

an input coupled to said processor means by said signal communication means for receiving an object description; and

, a memory coupled to said processor means by said signal communication means for storing data;

said object description system comprising;

object means, operatively coupled to said processor means by said signal communication means, including frame means operatively coupled to said processor means by said signal communication means for generating said mixed resolution, N-dimensional, object space, said frame means including,

means for interleaving the bits of coded attribute names of an object frame to generate an object descriptor and for interleaving the bits of a particular instance of frame data to generate an object selector; and

at least one register for storing said object frame for controlling the order of the interleaving of bits of said object frame by said interleaving means and for controlling the order of the interleaving of bits of said frame data by said interleaving means;

whereby, said data storage locations of said apparatus, when configured as mixed-resolution, N-dimensional, object spaces, are logically addressed and manipulated by fundamental data storage operations without converting mixed-radix expressions to and from unit expressions imposed by the fixed-radix architecture of general purpose computing devices for a mixed-radix mode of operating said computing device.

11. The apparatus as set forth in claim 10 further including:

selector means coupled to said frame means and coupled to said processor means by said signal communication means for selecting elements and paths of said memory configured as said mixed-resolution, N-dimensional, object space, wherein said selector means includes

at least one register for storing an object selector; and

means for changing the sense of particular object selector bits forming attribute relations between particular elements of said of said memory configured as said mixed-resolution, N-dimensional, object space; and

region means coupled to said frame means and coupled to said processor means by said signal communication means for manipulating regions comprising a plurality of related elements of said memory configured as said mixed-resolution, N-dimensional, object space, wherein said region means includes

at least one register for storing an object selector; and

means for suppressing particular object selector bits forming a region comprising a plurality of related elements of said memory configured as said mixed-resolution, N-dimensional, object space.

12. The apparatus as set forth in claim 10 or 11 wherein said computing device includes display means for visualizing problem space descriptions as spatial locations for a mixed-resolution, N-dimensional, object space, said display means operatively coupled to said processor means and said inputting means by said signal communication means, whereby a user interactively controls the internal operation of said computing device.

13. The apparatus as set forth in claim 10 or 11 for controlling the logical manipulation of data storage locations of at least one memory of a plurality of computing devices configured as at least one mixed-resolution, N-dimensional, object space, wherein the apparatus includes a special purpose multiprocessor having a mixed-radix logical architecture, wherein representations of said at least one mixed-resolution, N-dimensional, object space exist in at least one memory.

14. The apparatus as set forth in claim 10 or 11 wherein a plurality of object description systems are operatively coupled in various logical configurations dictated by the conceptual problem domain, enabling at least one of concurrent manipulation of a plurality of object space descriptions and concurrent manipulation of a plurality of views of a particular object space description.