User scheduled direct memory access using virtual addresses

• US 5,301,287 A
• Filed: 02/16/1993
• Issued: 04/05/1994
• Est. Priority Date: 03/12/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Morrissey, Thomas P., Herrell, Russ W.
• Primary Examiner(s): Kulik, Paul V.
• Assistant Examiner(s): AMSBURY, WAYNE P
• Application Number:
  US08/018,479
• Time in Patent Office: 413 Days
• Field of Search: 395/325, 395/600, 395/400, 395/425
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: Y10S 707/99945 Object-oriented database structure processing
• CPC Class Codes: Y10S 707/99948 Application of database or data structure, e.g. distributed, multimedia, or image

Abstract

The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, translates virtual addresses from the user applications program to physical addresses, and retrieves blocks of data from the main system memory at the request of the user'"'"'s code, rather than at the request of the kernel code of the host system. This is accomplished by representing the data processing commands of the user and the data associated therewith as respective command/pointer packets comprised of data processing commands and virtual pointers to the associated data in virtual memory space of the user'"'"'s host system. The virtual pointers of the command/pointer packets may then be translated to physical pointers for purposes of identifying physical addresses within the main memory at which the associated data is located. The associated data may then be read from the physical address in the main memory without interrupting the host processor. Techniques are also disclosed whereby the attributes of virtual memory systems such as page fault and access fault correction may be maintained in conjunction with the user scheduled DMA technique of the invention.

Claims

1. An interface device for transferring data associated with data processing commands directly between a user'"'"'s host system having a main memory and an external data processing system in response to user commands without direct host operating system management during individual memory transfer transactions, comprising:

means for representing said data processing commands and associated data as command/pointer packets comprising said data processing commands and virtual pointers to said associated data in virtual memory space of the user'"'"'s host system;

means on said interface device, coupled to said virtual memory space, for directly translating said virtual pointers of said command/pointer packets to physical pointers which identify physical addresses within said main memory at which said associated data is located; and

means on said interface device for transferring said associated data from and to said main memory at said physical addresses.

2. A device as in claim 1, wherein said external data processing system comprises a communications network.

3. A device as in claim 1, wherein said external data processing system comprises a graphics subsystem of said user'"'"'s host system.

4. A device as in claim 3, wherein said data processing commands comprise graphics commands and said associated data comprises graphics primitives.

5. A device as in claim 4, wherein said representing means comprises a user applications program operating on said user'"'"'s host system.

6. A device as in claim 5, wherein said translating means comprises a DMA processor having access to at least one shadow page table updated by a processor driven operating system of the user'"'"'s host system, said at least one shadow page table containing physical pointers corresponding to said virtual pointers.

7. A device as in claim 6, wherein said DMA processor has a user privileged shadow page table for each user controlled process of said host system.

8. A device as in claim 7, wherein said DMA processor includes a translation lookaside buffer for storing virtual to physical translations found during recent accesses by the DMA processor to said shadow page table.

9. A device as in claim 8, further comprising additional data storage means for storing data, said DMA processor interrupting said processor driven operating system of the user'"'"'s host system, when said translating means receives an indication that a required translation is not located in the shadow page table, so that said processor driven operating system can operate a fault algorithm for locating and swapping said associated data between said additional data storage means and said main memory, so that the processor driven operating system can then create the required translation and place said required translation into the shadow page table.

10. A device as in claim 7, wherein translations in said shadow page table are created and updated by said processor driven operating system in response to indications from said DMA processor that translations required to access associated data in main memory are not present in the shadow page table in said main memory.

11. A device as in claim 10, further comprising synchronizing means for synchronizing reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said user'"'"'s host system to reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said transferring means so that data consistency in main memory is maintained.

12. A device as in claim 7, wherein said translating means further comprises a command/pointer packet buffer for sequentially storing said command/pointer packets for parsing by said DMA processor.

13. A device as in claim 7, wherein said transferring means comprises DMA state means responsive to said DMA processor for initiating a read or a write of said associated data from or to said main memory.

14. A device as in claim 13, wherein said DMA state means comprises a register written by said DMA processor to indicate a starting data buffer address for said associated data in said main memory.

15. A device as in claim 14, wherein said starting data buffer address represents a work buffer in said main memory in which said command/pointer packets are stored.

16. A device as in claim 7, wherein said transferring means comprises a bidirectional bus buffer and an input/output bus for connecting said translating means to said user'"'"'s host system and said main memory.

17. An interface device for transferring graphics primitives associated with graphics commands directly between a user'"'"'s host system having a main memory and a graphics subsystem in response to user commands without direct host operating system management during individual memory transfer transactions, comprising:

means for representing said graphics commands and graphics primitives as command/pointer packets comprising said graphics commands and virtual pointers to said graphics primitives in virtual memory space of the user'"'"'s host system;

means on said interface device, coupled to said virtual memory space, for directly translating said virtual pointers to physical pointers which identify physical addresses within said main memory at which said graphics primitives are located; and

means on said interface device for transferring said graphics primitives from and to said main memory at said physical addresses.

18. A device as in claim 17, wherein said representing means comprises a user applications program operating on said user'"'"'s host system and said translating means comprises a DMA processor having access to at least one shadow page table updated by a processor driven operating system of the user'"'"'s host system, said at least one shadow page table containing physical pointers corresponding to said virtual pointers.

19. A device as in claim 18, wherein said DMA processor has a user privileged shadow page table for each user controlled process of said host system.

20. A device as in claim 19, wherein said DMA processor includes a translation lookaside buffer for storing translations found during recent accesses by the DMA processor to said shadow page table.

21. A device as in claim 20, further comprising additional data storage means for storing data, said DMA processor interrupting said processor driven operating system, when said translating means receives an indication that a required translation is not in said shadow page table, so that said processor driven operating system can operate a fault algorithm for locating and swapping said graphics primitives between said additional data storage means and said memory, so that the processor driven operating system can then create the required translation and place said required translation into the shadow page table.

22. A device as in claim 19, wherein translations between virtual pointers to physical pointers of associated graphics primitives in said shadow page table are created and updated by said processor driven operating system in response to indications from said DMA processor that translations required to access associated graphics primitives in main memory are not in said shadow page table.

23. A device as in claim 22, further comprising synchronizing means for synchronizing reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said user'"'"'s host system to reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said transferring means so that data consistency in main memory is maintained.

24. A device as in claim 19, wherein said translating means further comprises a command/pointer packet buffer for sequentially storing said command/pointer packets for parsing by said DMA processor.

25. A device as in claim 19, wherein said transferring means comprises DMA state means responsive to said DMA processor for initiating a read or a write of said graphics primitives from or to said main memory.

26. A device as in claim 25, wherein said DMA state means comprises a register written by said DMA processor to indicate a starting data buffer address for said graphics primitives in said main memory.

27. A device as in claim 26, wherein said starting data buffer address represents a work buffer in said main memory in which said command/pointer packets are stored.

28. A device as in claim 19, wherein said transferring means comprises a bidirectional bus buffer and an input/output bus for connecting said translating means to said user'"'"'s host system and said main memory.

29. An interface device for transferring graphics primitives associated with graphics commands directly between a user'"'"'s host system having a main memory and a graphics subsystem in response to user commands without direct host operating system management during individual memory transfer transactions, comprising:

means for representing said graphics commands and graphics primitives as command/pointer packets comprising said graphics commands and virtual pointers to said graphics primitives in virtual memory space of the user'"'"'s host system;

means on said interface device for translating said virtual pointers to physical pointers which identify physical addresses within said main memory at which said graphics primitives are located, said translating means comprising a DMA processor having access to a user privileged shadow page table for each user controlled process of said host system, each shadow page table being created and updated by a processor driven operating system of said user'"'"'s host system in response to an indication that translations required to access graphics primitives are not in said shadow page table so as to contain current translations of physical pointers corresponding to said virtual pointers, and a command/pointer packet buffer for sequentially storing said command/pointer packets for parsing by said DMA processor;

DMA state means responsive to said DMA processor for transferring said graphics primitives from and to said main memory at said physical addresses; and

synchronizing means for synchronizing reads and writes of said shadow page tables and user'"'"'s virtual memory space in main memory by said user'"'"'s host system to reads and writes of said shadow page tables and user'"'"'s virtual memory space in main memory by said DMA state means so that data consistency in main memory is maintained.

30. A method for providing direct memory access by an external data processing system to data stored in a main memory of a user'"'"'s host system in response to a plurality of user'"'"'s data processing commands without direct host operating system management during individual memory transfer transactions, comprising the steps of:

representing each of said user'"'"'s data processing commands and associated data as a command/pointer packet including a virtual pointer to said associated data in virtual memory space of said user in said user'"'"'s host system;

directly translating by an interface device said virtual pointer to a physical pointer which identifies a physical address within said main memory at which said associated data is located; and

accessing said main memory by said interface device at the physical address identified by said physical pointer in order to transfer data to and from said main memory.

31. A method as in claim 30, wherein said external data processing system comprises a graphics subsystem of said user'"'"'s host system, each of said user'"'"'s data processing commands is a graphics command and said associated data comprises graphics primitives.

32. A method as in claim 31, wherein said translating step by said interface device includes the steps of:

performing table lookup in a translation lookaside buffer to find a translation of said virtual pointer to a physical pointer which identifies a corresponding physical address in main memory of the data associated with each of said user'"'"'s data processing commands;

when said translation lookaside buffer does not contain said translation, searching a shadow page table in said main memory for said translation;

if said translation is found in said shadow page table, adding the virtual pointer to physical pointer translation to said translation lookaside buffer;

writing said corresponding physical address to an address register of a DMA state device; and

repeating said table lookup step to find a next translation.

33. A method as in claim 32, comprising the further steps of suspending said translating step and transmitting an interrupt to said user'"'"'s host system when at least one of a memory and a protection fault is encountered during said translating step.

34. A method as in claim 30, wherein said translating step includes the step of checking a shadow page table for a translation of said virtual pointer into said physical pointer.

35. A method as in claim 34, comprising the further step of updating said shadow page table by adding a required translation when at least one of a memory and protection fault is encountered during said translating step.

36. A method as in claim 35, comprising the further step of synchronizing reads and writes of said shadow page tables and user'"'"'s virtual memory space in main memory by said user'"'"'s host system to reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said reading and writing step so that data consistency in main memory is maintained.

37. A method for providing direct memory access by an external data processing system having an interface device with a DMA processor to data stored in a main memory of a user'"'"'s host system in response to a user'"'"'s data processing command without direct host operating system management during individual memory transfer transactions, comprising the steps of:

preapproving all direct memory accesses by said external data processing system requested by said user in said user'"'"'s data processing command by writing a shadow page table root address in the DMA processor;

assembling a plurality of command/pointer packets for each user process, each of said command pointer packets comprising a user'"'"'s data processing command and a virtual pointer in virtual memory space of the user'"'"'s host system to data in said main memory for use in processing of said user'"'"'s data processing commands;

storing each of said command/pointer packets in a buffer on said interface device for sequentially storing said command/pointer packets for parsing by said DMA processor;

parsing each command/pointer packet by said DMA processor to obtain said user'"'"'s data processing command and said virtual pointer;

writing said user'"'"'s data processing command to an input of said external data processing system;

translating said virtual pointer into a corresponding physical pointer which identifies a physical address in said main memory at which said data is located, said translating performed by said DMA processor on said interface device by accessing translation information stored in said shadow page table, indicated by said shadow table root address;

determining a word count identifying the word length of said data; and

transferring to an input of said external data processing system a number words of said data corresponding to said word count, said data transfer starting at an address in said main memory identified by said physical pointer, said data transfer controlled by a DMA state device responsive to said DMA processor, said DMA state device and said DMA processor located on said interface device.

38. A method as in claim 37, comprising the further step of flushing a cache memory of said main memory before said data transferring step is attempted in order to maintain data consistency.

39. A method as in claim 37, wherein said translating step includes the steps of:

performing table lookup in a translation lookaside buffer to find a translation of said virtual pointer to a physical pointer which identifies a corresponding physical address in main memory of the data associated with each of said user'"'"'s data processing commands;

when said translation lookaside buffer does not contain said translation, searching a shadow page table in said main memory for said translation;

if said translation is found in said shadow page table, adding the virtual pointer to physical pointer translation to said translation lookaside buffer;

writing said corresponding physical address to an address register of a DMA state device; and

repeating said table lookup step to find a next translation.

40. A method as in claim 37, comprising the further steps of suspending said translating step and transmitting an interrupt to said user'"'"'s host system when at least one of a memory and a protection fault is encountered during said translating step.

41. A method as in claim 37, wherein said translating step includes the step of checking a shadow page table for a translation of said virtual pointer into said physical pointer.

42. A method as in claim 41, comprising the further step of synchronizing reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said user'"'"'s host system to reads and writes of said shadow page table and user'"'"'s virtual memory space in main memory by said transferring means so that data consistency in main memory is maintained.