Data transfer control system between high speed main memory and input/output processor with a data mover

• US 5,301,351 A
• Filed: 01/13/1993
• Issued: 04/05/1994
• Est. Priority Date: 11/29/1988
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Jippo, Akira
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): SHAH, ALPESH
• Application Number:
  US08/003,685
• Time in Patent Office: 447 Days
• Field of Search: 395/500, 395/800, 395/250, 395/275, 395/425
• US Class Current: 709/233
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

In a data processing method of this invention, data having an amount of a designated total data transfer length is transferred from a data buffer in a data mover to a designated start address of a control memory at a data transfer rate of a control data transfer control unit. Data having an amount of a designated block data transfer length is transferred from the buffer in the data mover to a designated start address of a high-speed arithmetic memory at a data transfer rate of a high-speed data transfer control unit.

Claims

1. A data processing apparatus comprising:

a high speed arithmetic processor;

a control memory, receiving a channel program from said high speed arithmetic processor and storing said channel program;

a control processor, receiving a signal from said high speed arithmetic processor indicating that said channel program was sent to said control memory, and outputting a start signal;

an input/output processor receiving said start signal from said control processor, reading out said channel program from said control memory and outputting a start data transfer signal;

a memory device receiving said start data transfer signal from said input/output processor and outputting designated data to a first buffer in said control memory at a first transfer rate, wherein when all said designated data are transferred from said memory device to said first buffer, an end of transfer signal is sent from said input/output processor to said control processor, said control processor producing transfer control data from said channel program in response to said end of transfer signal;

a data mover receiving said transfer control data from said control processor; and

a second buffer in said data mover receiving said designated data at said first transfer rate from said control memory, under control of said data mover and transferring said received designated data from said second buffer at a second transfer rate, under control of said data mover, higher than said first transfer rate, to a high speed arithmetic memory.

3. The data processing apparatus as recited in claim 1, wherein said first transfer rate is equal to the rate of data transfer between said control processor and said control memory, and said second transfer rate is equal to the rate of data transfer between said high speed arithmetic processor and said high speed arithmetic memory.

2. A method for transferring data comprising the steps of:

transferring a channel program to a first memory unit in a first processor group from a processor in a second processor group;

signalling a control processor in said first processor group that said transferring step has occurred;

reading said channel program stored in said first memory unit by another processor in said first processor group in response to said signalling of transferring;

transferring designated data, in response to said reading of said channel program, from a secondary memory device in said first processor group to said first memory unit in said first processor group;

signalling said control processor that said transferring designated data step is complete;

reading said channel program stored in said first memory unit by said control processor in response to said signalling step of complete transferring; and

signalling a data mover to begin transferring data from said first memory unit of said first processor group to a second memory unit of said second processor group, in response to said reading by said control processor, wherein said designated data in said first memory unit of said first processor group is transferred at a first predetermined rate equal to a first rate of data transfer between said first processor group and said first memory unit in said first processor group to a buffer in said data mover, and said designated data is transferred from said buffer to said second memory unit of said second processor group at a second predetermined rate equal to a second rate of data transfer between said second processor group and said second memory unit in said second processor group.