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Data transfer control system between high speed main memory and input/output processor with a data mover

  • US 5,301,351 A
  • Filed: 01/13/1993
  • Issued: 04/05/1994
  • Est. Priority Date: 11/29/1988
  • Status: Expired due to Fees
First Claim
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1. A data processing apparatus comprising:

  • a high speed arithmetic processor;

    a control memory, receiving a channel program from said high speed arithmetic processor and storing said channel program;

    a control processor, receiving a signal from said high speed arithmetic processor indicating that said channel program was sent to said control memory, and outputting a start signal;

    an input/output processor receiving said start signal from said control processor, reading out said channel program from said control memory and outputting a start data transfer signal;

    a memory device receiving said start data transfer signal from said input/output processor and outputting designated data to a first buffer in said control memory at a first transfer rate, wherein when all said designated data are transferred from said memory device to said first buffer, an end of transfer signal is sent from said input/output processor to said control processor, said control processor producing transfer control data from said channel program in response to said end of transfer signal;

    a data mover receiving said transfer control data from said control processor; and

    a second buffer in said data mover receiving said designated data at said first transfer rate from said control memory, under control of said data mover and transferring said received designated data from said second buffer at a second transfer rate, under control of said data mover, higher than said first transfer rate, to a high speed arithmetic memory.

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