Method of encoding identification information on circuit dice using step and repeat lithography

• US 5,302,491 A
• Filed: 07/19/1993
• Issued: 04/12/1994
• Est. Priority Date: 12/20/1989
• Status: Expired due to Fees

• Current Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Seaborg, Charles, Akylas, Victor R.
• Primary Examiner(s): McCamish, Marion E.
• Assistant Examiner(s): ROSASCO, STEPHEN D
• Application Number:
  US08/093,446
• Time in Patent Office: 267 Days
• Field of Search: 430/311, 430/312, 430/313, 430/322, 430/394, 437/229
• US Class Current: 430/311
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 21/681 using optical controlling means
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/946 Step and repeat

Abstract

A method is disclosed whereby identification information can be encoded onto a plurality of circuit dice on a wafer to enable each of them to be distinguished from one another. An array of electrically readable identification elements, such as resistors, is disposed on each of the circuit dice during the circuit fabrication process. A first mask is then positioned over the each of the dice which completely covers all but the identification elements. A step and repeat mask is then selectively positioned over a particular element or elements in the array which identify a circuit die by its location on the wafer. The die is then exposed using a conventional step and repeat photolithographic process so that only the selected identification element or elements in the array will remain. The second mask is then stepped over the next circuit die on the wafer but is positioned over a different identification element or elements in the array. This process is repeated for all of the circuit dice on the wafer so that different identification elements remain for each circuit die to distinguish them from one another. Using the step and repeat process in this manner eliminates the necessity for individually coding the identification information into each of the circuit dice.

Claims

1. A method whereby formation of a predetermined circuit pattern on each of a plurality o circuit dies of a semiconductor wafer is accompanied by inclusion on each die of electrically detectable information for identifying said die, the dies all having the same rectangular dimensions and being in rectangular array in successive rows and columns;

said method comprising the steps of;

(a) forming on each of said dies in succession, by step-and-repeat lithography, said predetermined circuit pattern and a rectangular array of identical electrically detectable identification elements, said array constituting an identification array which is the same and at the same position on each die, the identification elements therein being in successive rows and columns analogous to the rows and columns of said die array, adjoining identification elements all having the same pitch distance (D);

the step-and-repeat lithography including positioning a first photomask over the die in a first column of a first row of the die array and subsequently successively repositioning the first photomask over each successive die in successive columns of successive rows of the die array, each said repositioning being by stepping the first photomask a stepping distance (W) from a present position thereof;

(b) modifying the identification array on each die so as to select, by retention or removable, one of the identification elements therein;

the position of the selected identification element in the identification array on any particular die constituting electrically detectable information for identifying said die;

said modification being performed by the steps of;

(i) forming a photosensitive resist on the identification arrays on all dies;

(ii) providing a second photomask having an aperture therein of dimensions matching corresponding dimensions of each identification element;

(iii) positioning the second photomask over the die in a first column of a first row of the die array so that the aperture in the second photomask registers with the identification element in a first column of a first row of the identification array on said die;

(iv) successively repositioning the second photomask over the identification array on each succeeding die in successive columns of successive rows of said die array, each said repositioning being by stepping the second photomask said stepping distance (W) augmented by said pitch distance (D), so that at each step the aperture in the second photomask registers with the identification element in a row and column of the identification array on the next succeeding die which corresponds to the row and column of said next succeeding die in the die array;

(v) during each of steps (iii) and (iv), subjecting the second photomask to radiation while the aperture therein is registered with an identification element, thereby photolithographically modifying the area of the photosensitive resist overlying said registered identification element; and

(vi) after completion of steps (iv) and (v) for all dies, developing said photosensitive resist so as to pattern it in accordance with the modified areas thereof, and using the patterned resist to select, by retention or removal, only those of the identification elements on which the modified areas of said resist had been formed;

whereby the identification array on each die is modified so that position of the selected identification element therein constitutes electrically detectable information for identifying such die.

2. A method as claimed in claim 1, wherein in step (b) and in sub-step (vi) thereof the selected identification element on each die is retained and all other identification elements in the identification array on such die are removed.

3. A method as claimed in claim 2, wherein the identification elements are resistors.

4. A method as claimed in claim 1, wherein in step (b) and in sub-step (vi) thereof, the selected identification element on each die is removed and all other identification elements in the identification array on such die are retained.

5. A method as claimed in claim 4, wherein the identification elements are resistors.

6. A process as claimed in claim 1, wherein the identification elements are resistors.

7. A method as claimed in claim 6, wherein in step (b) and sub-step (vi) thereof the selected identification elements on each die are removed and all other identification elements in the identification array on such die are retained.

8. A method as claimed in claim 7, wherein the identification elements are resistors.

9. A method as claimed in claim 6, wherein in step (b) and in sub-step (vi) thereof the selected identification elements on each die are retained and all other identification elements in the identification array on such die are removed.

10. A method as claimed in claim 15, wherein the identification elements are resistors.

11. A method whereby formation of a predetermined circuit pattern on each of a plurality of circuit dies of a semiconductor wafer is accompanied by inclusion on each die of electrically detectable information for identifying said die, the dies all having the same rectangular dimensions and being in rectangular array in successive rows and columns;

said method comprising the steps of;

(a) forming on each of said dies in succession, by step-and-repeat lithography, said predetermined circuit pattern and a rectangular array of identical electrically detectable identification elements, said array constituting an identification array which is the same and at the same position on each die, the identification elements therein respectively being in respective rows and respective columns corresponding to respective rows and respective columns of said die array, identification elements in adjoining rows and identification elements in adjoining columns all having the same pitch distance (V);

the step-and-repeat lithography including positioning a first photomask over the die in a first column and first row of the die array and subsequently successively repositioning the first photomask over each successive die in successive columns of successive rows of the die array, each said repositioning being by stepping the first photomask a stepping distance (W) from a present position thereof;

(b) modifying the identification array on each die so as to select, by retention or removable, an identification element in a row of said array and an identification in a column of said array, the positions of the selected row and column identification elements in the identification array on any particular die constituting electrically detectable information uniquely identifying said die, said modification being performed by the steps of;

(i) forming a photosensitive resist on the identification arrays on all dies;

(ii) providing a second photomask having a row aperture therein and a column aperture therein each of dimensions matching the corresponding dimensions of each identification element;

(iii) positioning the second photomask over the die in a first column of a first row of the die array so that the row aperture in the second photomask registers with the identification element in a first row of the identification array on said die and the column aperture in the second photomask registers with the identification element in a first column of the identification array on said die;

(iv) successively repositioning the second photomask over the identification array on each next succeeding die in successive columns of successive rows of said die array, each said repositioning being performed by stepping the second photomask said stepping distance (W) augmented by said pitch distance (D), so that at each step the row and column apertures in the second photomask respectively register with identification elements respectively in a row and column of the identification array on the next succeeding die which correspond to the row and column of said next succeeding die in said die array;

(v) during each of steps (iii) and (iv), subjecting the second photomask to radiation while the apertures therein are registered with identification elements, thereby photolithographically modifying the areas of the photosensitive resist overlying said registered identification elements; and

(vi) after completion of steps (iv) and (v) for all dies, developing said photosensitive resist so as to pattern it in accordance with the modified areas thereof, and using the patterned resist to select, by retention or removal, only those of the identification elements on which the modified areas of said resist had been formed;

whereby the identification array on each die is modified so that the positions of the selected identification elements therein constitute electrically detectable information for identifying such die.

12. A method as claimed in claim 11, wherein the identification elements are resistors.