Programmable chip enable logic function

• US 5,303,181 A
• Filed: 10/20/1992
• Issued: 04/12/1994
• Est. Priority Date: 11/08/1985
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Stockton, David W.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/963,468
• Time in Patent Office: 539 Days
• Field of Search: 365/96, 365/225.7, 365/189.08, 365/191, 365/230.03, 365/230.04, 364/716, 340/825.83, 340/825.84
• US Class Current: 365/96
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays

Abstract

A programmable chip enable provides for enabling or disabling an integrated circuit in response to a selected one of a plurality of logic signals. In a specific application, the programmable enable function is used in combination with a plurality of field programmable memory devices. The enable functions of the respective devices are programmed to prevent simultaneous enablement of the memory devices which have their outputs connected together.

Claims

1. A memory circuit arrangement, comprising:

a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and

a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and

wherein, at least one of the respective outputs of said first and second memory devices are connected together;

wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

2. An integrated circuit according to claim 1, wherein said programmable element is a fuse.

3. An integrated circuit according to claim 1, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

4. An integrated circuit according to claim 1, wherein said logic element is an Exclusive OR gate.

5. A field programmable memory device, comprising:

a first array of memory elements;

a second array of memory elements;

a plurality of inputs and outputs for accessing the memory elements in each of the arrays;

an enable input for receiving first and second enable signals from an external source; and

programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals;

wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together;

wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

6. An integrated circuit according to claim 5, wherein said programmable element is a fuse.

7. An integrated circuit according to claim 5, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

8. An integrated circuit according to claim 5, wherein said logic element is an Exclusive OR gate.

9. A memory circuit arrangement, comprising:

a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and electrically programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and

a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and electrically programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and

wherein, at least one of the respective outputs of said first and second memory devices are connected together.

10. A field programmable memory device, comprising:

a first array of memory elements;

a second array of memory elements;

a plurality of inputs and outputs for accessing the memory elements in each of the arrays;

an enable input for receiving first and second enable signals from an external source; and

electrically programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals;

wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together.