Redundant memory device having a memory cell and electrically breakable circuit having the same dielectric film

• US 5,303,199 A
• Filed: 02/19/1991
• Issued: 04/12/1994
• Est. Priority Date: 02/19/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ishihara, Hiroshi, Tanigawa, Makoto
• Primary Examiner(s): LEE, BENNY T
• Application Number:
  US07/656,441
• Time in Patent Office: 1,148 Days
• Field of Search: 365/96, 365/102, 365/149, 365/200, 365/225.7, 257/530, 257/665
• US Class Current: 365/225.7
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An easily circuit-programmable semiconductor device which comprises a dynamic random access memory (DRAM) unit, a redundancy circuit and a connection between them, the DRAM unit having as a capacitor a dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer and the connection having, as a member for programming the redundancy circuit, an electrically breakable dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer.

Claims

1. A semiconductor device which comprises a dynamic random access memory (DRAM) unit and a redundancy circuit therefor,

the DRAM unit being comprised of a MOS transistor and a capacitor connected to the MOS transistor, the capacitor being comprised of a dielectric film interposed between two electrodes, the dielectric film being comprised of a silicon oxide/silicon/nitride/silicon oxide composite layer,

the redundancy circuit having an electrically breakable dielectric film interposed between two electrodes, the electrically breakable dielectric film being the same film as the dielectric film of a silicon/oxide/silicon nitride/silicon oxide composite layer and interposed at a connection between the DRAM unit and the redundancy circuit,

whereby the application of a predetermined voltage to the two electrodes between which the breakable dielectric film is interposed breaks the breakable dielectric film and electrically connects the DRAM unit and the redundancy circuit.

2. The semiconductor device of claim 1 in which both of the dielectric film and the electrically breakable dielectric film have a respective thickness which provides a dielectric constant equivalent to a SiO₂ film having a thickness of 50 to 120 Å

.

3. The semiconductor device of claim 1 in which the predetermined voltage results in an electric field of at least 12 MV.

4. The semiconductor device of claim 1 in which the dielectric film of the DRAM unit and the electrically breakable dielectric film are integrally connected to each other.

5. The semiconductor device of claim 1 in which each silicon oxide of the composite layers is a thermally oxidized silicon oxide layer having a thickness of 10 to 50 Å

.