High performance asynchronous transfer mode switch

• US 5,303,232 A
• Filed: 04/03/1991
• Issued: 04/12/1994
• Est. Priority Date: 05/25/1990
• Status: Expired due to Term

• Current Assignee: Ericsson AB (Telefonaktiebolaget LM Ericsson)
• Original Assignee: GPT Ltd.
• Inventors: Jeffrey, Mark T., Proctor, Richard J., Maddern, Thomas S., Philip, Alexander
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Nguyen, Chau T.
• Application Number:
  US07/679,768
• Time in Patent Office: 1,105 Days
• Field of Search: 370/60, 370/94.1, 370/54, 370/61, 370/60.1, 370/58.1-58.3
• US Class Current: 370/398
• CPC Class Codes: G02F 1/295 Analog deflection from or in an optical waveguide structure]
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/565 Sequence integrity
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/1538 Cell slicing
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics

Abstract

The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 . . . 1SN) each for receiving a digital data transmission stream (DS1 . . . 256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages.

Claims

1. An Asynchronous Transfer Mode Switch having a plurality of input stages each for receiving a digital data transmission stream consisting of a series of cells, a cell comprising data and a header containing control data from which the destination of the cell can be determined, a plurality of central stages connected to the input stages to receive the data from the input stages to be switched across the switch, each central stage including a central switch, and a plurality of output stages each connected to the central stages, and wherein for every input stage there is a route to every central stage for the transmission of data, and from every central stage there is a route to every output stage, and wherein each input stage includes a circuit for determining the destination of the cells of that data stream, a circuit for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages, means for storing the cell elements sequentially, means for requesting from a central stage, in response to receipt of a cell within the input stage, permission to transmit a cell element in the series and after a predetermined delay a further request for the same destination point provided that the stored cell elements are derived from the same cell, means for receiving a response output from the central stage in response to the request as to the availability of the requested destination between the sending of requests so that the sequence of sending a request of one cell element is interleaved with the response to the request for the preceding cell element, and means for transmitting each cell element to the central stage after a second predetermined delay from the receipt of a positive response therefrom.

2. A switch as claimed in claim 1 and further comprising a plurality of element queues operative to store therein successive cell elements, each element queue being connected to a plurality of parallel element sender circuits, the element sender circuits operating under the control of a pathfinder control circuit which examines the routing information carried by each cell element and sends requests to the central switch for a number of data elements stored in each cell element queue.

3. A switch as claimed in claim 2 wherein each pathfinder control circuit sends a series of spaced requests to the central stage, each request being for a window for a cell element in the element queue.

4. A switch as claimed in claim 3 in which to maintain cell sequence integrity across the switch the input and output central stage accesses are rotated in steps so that for any cell input to the switch there is a constant storage delay in the central stage.