Continuous synaptic weight update mechanism

• US 5,303,329 A
• Filed: 12/10/1991
• Issued: 04/12/1994
• Est. Priority Date: 12/10/1991
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute, Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Platt, John C., Mead, Carver A., Anderson, Janeen D. W.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): DOWNS, ROBERT W
• Application Number:
  US07/805,324
• Time in Patent Office: 854 Days
• Field of Search: 307/201, 395/24, 364/807, 365/49, 365/185, 365/529, 365/570
• US Class Current: 706/33
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.

Claims

1. A continuous synaptic weight-update device comprising:

a single floating node having a capacitance associated therewith;

first and second signal input lines;

first and second error input lines;

electron tunneling means, connected to said floating node, for tunneling electrons from said floating node;

hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node;

first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference voltage when it is desired to remove electrons from said floating node;

second driving means for driving voltages on said second signal input line and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node;

first control means, responsive to the product of said votlages on said first signal input line and said first error input line, for activating said electron tunneling means; and

second control means, responsive to the product of said voltages on said second signal input line and said second error input line, for activating said hot electron injecting means.

2. The continuous synaptic weight-update device of claim 1 wherein said first control means comprises a first MOS transistor having a source and drain connected between said first signal input line and said electron tunneling means and a gate connected to said first error input line and a second MOS transistor having a source and drain connected between said first error input line and said electron tunneling means and a gate connected to said first signal input line and wherein said second control means comprises a third MOS transistor having a source and drain connected between said second signal input line and said hot electron injecting means and a gate connected to said second error input line and a fourth MOS transistor having a source and drain connected between said second error input line and said hot electron injecting means and a gate connected to said second signal input line.

3. The continuous synaptic weight-update device of claim 1 wherein said first driving means includes a first bi-directional current source for injecting a first current onto said first signal input line, said first current derived from a source of input signals, and a second bi-directional current source for injecting a second current onto said first error input line, said second current derived from a source of error signals, and wherein said second driving means includes a third bi-directional current source for injecting a third current onto said second signal input line, said third current derived from said source of input signals, and a fourth bi-directional current source for injecting a fourth current onto said fourth signal input line, said fourth current derived from said source of error signals.

4. The continuous synaptic weight-update device of claim 3 wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth transconductance amplifiers, one input of said first and third transconductance amplifiers connected to said source of input signals, the inputs of said second and fourth transconductance amplifiers comprising said source of error signals.

5. The continuous synaptic weight-update device of claim 1 wherein:

said first driving means includes a first bi-directional current source for injecting a first current onto a first signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first input signal node, and means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first error input node, said second current derived from a source of error signals, a third diode-connected MOS transistor connected between said first reference voltage and said first error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first error input node, and means responsive to the voltage on said first error input node for driving a voltage onto said first error input line; and

said second driving means includes a third bi-directional current source for injecting a third current onto a second signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between said third reference voltage and said second input signal node, a sixth diode-connected MOS transistor connected between a fourth reference voltage and said second input signal node, and means responsive to the voltage on said second input signal node for driving a votlage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference votlage and said second error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second error signal node, and means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line.

6. The continuous synaptic weight-update device of claim 1 wherein said floating node comprises the gate of at least one MOS transistor in a synaptic element.

7. A synaptic element comprising:

at least one MOS transistor including a drain, a source, and a gate, the drain of said MOS transistor connected to an output summing node;

a single floating node having a capacitance associated therewith, said floating node comprising at least a portion of said gate of said at least one MOS transistor;

first and second signal input lines;

first and second error input lines;

electron tunneling means, connected to said floating node, for tunneling electrons from said floating node;

hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node;

first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference votlage when it is desired to remove electrons from said floating node;

second driving means for driving voltages on said second signal input lines and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node;

first control means, responsive to signals on said first signal input line and said first error input line, for activating said electron tunneling means; and

second control means, responsive to signals on said second signal input line and said second error input line, for activating said hot electron injecting means.

8. The synaptic element of claim 7 wherein said first control means comprises a first MOS transistor having a source and drain connected between said first signal input line and said electron tunneling means and a gate connected to said first error input line and a second MOS transistor having a source and drain connected between said first error input line and said electron tunneling means and a gate connected to said first signal input line and wherein said second control means comprises a third MOS transistor having a source and drain connected between said second signal input line and said hot electron injecting means and a gate connected to said second error input line and a fourth MOS transistor having a source and drain connected between said second error input line and said hot electron injecting means and a gate connected to said second signal input line.

9. The continuous synaptic weight-update device of claim 7 wherein:

said first driving means includes a first bi-directional current source for injecting a first current onto a first signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first input signal node, and means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first error input node, said second current derived from a source of error signals, a third diode-connected MOS transistor connected between said first reference voltage and said first error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first error input node, and means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, and

said second driving means includes a third bi-directional current source for injecting a third current onto a second signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between a third reference voltage and said second input signal node, a sixth diode-connected MOS transistor connected between a fourth second reference voltage and said second input signal node, and means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference voltage and said second error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second error signal node, and means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line.

10. The continuous synaptic weight-update device of claim 9, further including summing means for generating an output voltage from the current present on said output summing node and wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth differential transconductance amplifiers, one input of said first and third differential transconductance amplifiers connected to said source of input signals, one input of said second and fourth differential transconductance amplifiers connected to the output of said summing means and the other input of said second and fourth differential transconductance amplifiers connected to a source of desired-output signals.

11. The synaptic element of claim 9 wherein said first, second, third, and fourth bi-directional current sources comprise transconductance amplifiers.

12. The synaptic element of claim 9 wherein said means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, said means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, said means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and said means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line comprise buffer amplifiers.

13. A synaptic array comprising:

a plurality of synaptic elements, each of said synaptic elements associated with a row and a column of said array, each of said synaptic elements including at least one MOS transistor having a drain, a source, and a gate, each synaptic element having an output node;

a continuous weight-update structure associated with each of said synaptic elements, each of said continuous weight-update structures including a single floating node having a capacitance associated therewith, said floating node comprising at least a portion of said gate of said at least one MOS transistor, first and second signal input nodes, first and second error input nodes, electron tunneling means, connected to said floating node, for tunneling electrons from said floating node, hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node, first control means, responsive to signals on said first signal input node and said first error input node, for activating said electron tunneling means, and second control means, responsive to signals on said second signal input node and said second error input node, for activating said hot electron injecting means;

a first signal input line and a second signal input line associated with each row in said array, said first signal input line of each row connected to the first signal input node of each of said synaptic elements associated with that row and said second signal input line of each row connected to the second signal input node of each of said synaptic elements associated with that row;

a first error input line and a second error input line associated with each column in said array, said first error input line of each column connected to the first error input node of each of said synaptic elements associated with that column and said second error input line of each column connected to the second error input node of each of said synaptic elements associated with that column;

a plurality of first driving means, one of said plurality of first driving means associated with each row and column of said array, for driving voltages on said first signal input line and said first error input line of its row and column in opposite directions with respect to a first reference voltage when it is desired to remove electrons from the floating node in the one of said synaptic elements located at the intersection of said row and column;

a plurality of second driving means, one of said plurality of second driving means associated with each row and column in said array, for driving voltages on said second signal input line and said second error input line of its row and column in opposite directions with respect to a second reference voltage when it is desired to place electrons onto the floating node in the one of said synaptic elements located at the intersection of said row and column; and

an output summing line associated with each column in said array, each output summing line connected to the output nodes of each of said plurality of synaptic elements associated with that column.

14. The array of claim 13 wherein each of said first driving means includes a first bi-directional current source for injecting a first current onto said first signal input line for its row in said array, said first current derived from a first source of input signals, a second bi-directional current source for injecting a second current onto said first error input line for its column in said array, said second current derived from a first source of error signals, and wherein each of said second driving means includes a third bi-directional current source for injecting a third current onto said second signal input line for its row in said array, said third current derived from a second source of input signals, and a fourth bi-directional current source for injecting a fourth current onto said second error input line for its column in said array, said fourth current derived from a second source of error signals.

15. The array of claim 13 wherein:

each of said first driving means includes a first bi-directional current source for injecting a first current onto a first driver signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first driver signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first driver input signal node, and means responsive to the voltage on said first driver input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first driver error input node, said second current derived from a source of error signals, a third diode-connected MOS transistor connected between said first reference voltage and said first driver error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first driver error input node, and means responsive to the voltage on said first driver error input node for driving a voltage onto said first error input line, and

each of said second driving means includes a third bi-directional current source for injecting a third current onto a second driver signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between a third reference voltage and said second driver input signal node, a sixth diode-connected MOS transistor connected between a fourth reference voltage and said second driver input signal node, and means responsive to the voltage on said second driver input signal node for driving a voltage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth driver signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference voltage and said second driver error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second driver error signal node, and means responsive to the voltage on said second driver error signal node for driving a voltage onto said second error input line.

16. The array of claim 15, further including summing means for generating an output voltage from the currents present on each of said output summing lines and wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth differential transconductance amplifiers, one input of said first and third differential transconductance amplifiers connected to said source of input signals, one input of said second and fourth differential transconductance amplifiers connected to the output of said summing means and the other input of said second and fourth differential transconductance amplifiers connected to a source of desired-output signals.

17. The synaptic element of claim 15 wherein said means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, said means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, said means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and said means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line. comprise buffer amplifiers.

18. A continuous synaptic weight-update device comprising:

a single floating node having a capacitance associated therewith;

first and second signal input lines;

first and second error input lines;

electron tunneling means, connected to said floating node, for tunneling electrons from said floating node;

hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node;

first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference voltage when it is desired to remove electrons from said floating node;

second driving means for driving voltages on said second signal input line and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node;

a first MOS transistor having a source and drain connected between said first signal input line and said electron tunneling means and a gate connected to said first error input line and a second MOS transistor having a source and drain connected between said first error input line and said electron tunneling means and a gate connected to said first signal input line;

a third MOS transistor having a source and drain connected between said second signal input line and said hot electron injecting means and a gate connected to said second error input line and a fourth MOS transistor having a source and drain connected between said second error input line and said hot electron injecting means and a gate connected to said second signal input line; and

said first and second MOS transistors formed in a well structure, said well structure biased at a fixed voltage higher than the voltage required for appreciable electron tunneling to said floating node and said first reference voltage held at a value larger than that required to excite appreciable tunneling.

19. The continuous synaptic weight-update device of claim 18 wherein said first driving means includes a first bi-directional current source for injecting a first current onto said first signal input line, said first current derived from a source of input signals, and a second bi-directional current source for injecting a second current onto said first error input line, said second current derived from a source of error signals, and wherein said second driving means includes a third bi-directional current source for injecting a third current onto said second signal input line, said third current derived from said source of input signals, and a fourth bi-directional current source for injecting a fourth current onto said fourth signal input line, said fourth current derived from said source of error signals.

20. The continuous synaptic weight-update device of claim 19 wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth transconductance amplifiers, one input of said first and third transconductance amplifiers connected to said source of input signals, the inputs of said second and fourth transconductance amplifiers derived from said source of error signals.

21. The continuous synaptic weight-update device of claim 18 wherein:

said first driving means includes a first bi-directional current source for injecting a first current onto a first signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first input signal node, and means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first error input node, said second current derived from a source of error signals a third diode-connected MOS transistor connected between said first reference voltage and said first error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first error input node, and means responsive to the voltage on said first error input node for driving a voltage onto said first error input line; and

said second driving means includes a third bi-directional current source for injecting a third current onto a second signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between said a third reference voltage and said second input signal node, a sixth diode-connected MOS transistor connected between a fourth reference voltage and said second input signal node, and means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference voltage and said second error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second error signal node, and means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line.

22. The synaptic element of claim 21 wherein said means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, said means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, said means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and said means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line. comprise buffer amplifiers.

23. The continuous synaptic weight-update device of claim 18 wherein said floating node comprises the gate of at least one MOS transistor in a synaptic element.

24. A synaptic element comprising:

at least one MOS transistor including a drain, a source, and a gate, the drain of said MOS transistor connected to an output summing node;

a single floating node having a capacitance associated therewith, said floating node comprising at least a portion of said gate of said at least one MOS transistor;

first and second signal input lines;

first and second error input lines;

electron tunneling means, connected to said floating node, for tunneling electrons from said floating node;

hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node;

a first MOS transistor having a source and drain connected between said first signal input line and said electron tunneling means and a gate connected to said first error input line and a second MOS transistor having a source and drain connected between said first error input line and said electron tunneling means and a gate connected to said first signal input line;

a third MOS transistor having a source and drain connected between said second signal input line and said hot electron injecting means and a gate connected to said second error input line and fourth MOS transistor having a source and drain connected between said second error input line and said hot electron injecting means and a gate connected to said second signal input line; and

said first and second MOS transistors formed in a well structure, said well structure biased at a fixed voltage higher than the voltage required for appreciable electron tunneling to said floating node and said first reference voltage held at a value larger than that required to excite appreciable tunneling.

25. The continuous synaptic weight-update device of claim 24 wherein:

said first driving means includes a first bi-directional current source for injecting a first current onto a first signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first input signal node, and means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first error input node, said second current derived from a source of error signals, a third diode-connected MOS transistor connected between said first reference voltage and said first error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first error input node, and means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, and

said second driving means includes a third bi-directional current source for injecting a third current onto a second signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between a third reference voltage and said second input signal node, a sixth diode-connected MOS transistor connected between a fourth reference voltage and said second input signal node, and means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference voltage and said second error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second error signal node, and means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line.

26. The continuous synaptic weight-update device of claim 25, further including summing means for generating an output voltage from the current present on said output summing node and wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth differential transconductance amplifiers, one input of said first and third differential transconductance amplifiers connected to said source of input signals one input of said second and fourth differential transconductance amplifiers connected to the output of said summing means and the other input of said second and fourth differential transconductance amplifiers connected to a source of desired-output signals.

27. The synaptic element of claim 25 wherein said first, second, third, and fourth bi-directional current sources comprise transconductance amplifiers.

28. The synaptic element of claim 25 wherein said means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, said means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, said means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and said means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line comprise buffer amplifiers.

29. A synaptic array comprising:

a plurality of synaptic elements, each of said synaptic elements associated with a row and a column of said array, each of said synaptic elements including at least one MOS transistor having a drain, a source, and a gate, each synaptic element having an output node;

a continuous weight-update structure associated with each of said synaptic elements, each of said continuous weight-update structures including a single floating node having a capacitance associated therewith, said floating node comprising at least a portion of said gate of said at least one MOS transistor, first and second signal input nodes, first and second error input nodes, electron tunneling means, connected to said floating node, for tunneling electrons from said floating node, hot electron injecting means, connected to said floating node, for injecting hot electrons onto said floating node, a first MOS transistor having a source and drain connected between said first signal input node and said electron tunneling means and a gate connected to said first error input node, a second MOS transistor having a source and drain connected between said first error input node and said electron tunneling means and a gate connected to said first signal input node, a third MOS transistor having a source and drain connected between said second signal input node and said hot electron injecting means and a gate connected to said second error input node, a fourth MOS transistor having a source and drain connected between said second error input node and said hot electron injecting means and a gate connected to said second signal input node, said first, second, third, and fourth MOS transistors formed in a well structure, said well structure biased at a fixed voltage higher than the voltage required for appreciable electron tunneling to said floating node and said second reference voltage held at a value larger than that required to excite appreciable tunneling;

a first signal input line and a second signal input line associated with each row in said array, said first signal input line of each row connected to the first signal input node of each of said synaptic elements associated with that row and said second signal input line of each row connected to the second signal input node of each of said synaptic elements associated with that row;

a first error input line and a second error input line associated with each column in said array, said first error input line of each column connected to the first error input node of each of said synaptic elements associated with that column and said second error input line of each column connected to the second error input node of each of said synaptic elements associated with that column;

a plurality of first driving means, one of said plurality associated with each row and column of said array, for driving voltages on said first signal input line and said first error input line of its row and column in opposite directions with respect to a first reference voltage when it is desired to remove electrons from the floating node in the one of said synaptic elements located at the intersection of said row and column;

a plurality of second driving means, one of said plurality associated with each row and column in said array, for driving voltages on said second signal input line and said second error input line of its row and column in opposite directions with respect to a second reference voltage when it is desired to place electrons onto the floating node in the one of said synaptic elements located at the intersection of said row and column;

an output summing line associated with each column in said array, each output summing line connected to the output nodes of each of said plurality of synaptic elements associated with that column.

30. The array of claim 29 wherein each of said first driving means includes a first bi=directional current source for injecting a first current onto said first signal input line for its row in said array, said first current derived from a first source of input signals, a second bi-directional current source for injecting a second current onto said first error input line for its column in said array, said second current derived from a first source of error signals, and wherein each of said second driving means includes a third bi-directional current source for injecting a third current onto said second signal input line for its row in said array, said third current derived from a second source of input signals ,and a fourth bi-directional current source for injecting a fourth current onto said second error input line for its column in said array, said fourth current derived from a second source of error signals.

31. The array of claim 29 wherein:

each of said first driving means includes a first bi-directional current source for injecting a first current onto a first driver signal input node, said first current derived from a source of input signals, a first diode-connected MOS transistor connected between a first reference voltage and said first driver signal input node, a second diode-connected MOS transistor connected between a second reference voltage and said first driver input signal node, and means responsive to the voltage on said first driver input signal node for driving a voltage onto said first signal input line, and a second bi-directional current source for injecting a second current onto a first driver error input node, said second current derived from a source of error signals, a third diode-connected MOS transistor connected between said first reference voltage and said first driver error input node, a fourth diode-connected MOS transistor connected between said second reference voltage and said first driver error input node, and means responsive to the voltage on said first driver error input node for driving a voltage onto said first error input line, and

each of said second driving means includes a third bi-directional current source for injecting a third current onto a second driver signal input node, said third current derived from said source of input signals, a fifth diode-connected MOS transistor connected between a third reference voltage and said second driver input signal node, a sixth diode-connected MOS transistor connected between a fourth reference voltage and said second driver input signal node, and means responsive to the voltage on said second driver input signal node for driving a voltage onto said second signal input line, and a fourth bi-directional current source for injecting a fourth current onto a fourth driver signal input node, said fourth current derived from said source of error signals, a seventh diode-connected MOS transistor connected between said third reference voltage and said second driver error input node, an eighth diode-connected MOS transistor connected between said fourth reference voltage and said second driver error signal node, and means responsive to the voltage on said second driver error signal node for driving a voltage onto said second error input line.

32. The array of claim 31, further including summing means for generating an output voltage from the currents present on each of said output summing lines and wherein said first, second, third, and fourth bi-directional current sources comprise first, second, third, and fourth differential transconductance amplifiers, one input of said first and third differential transconductance amplifiers connected to said source of input signals, one input of said second and fourth differential transconductance amplifiers connected to the output of said summing means and the other input of said second and fourth differential transconductance amplifiers connected to a source of desired-output signals.

33. The synaptic element of claim 31 wherein said means responsive to the voltage on said first input signal node for driving a voltage onto said first signal input line, said means responsive to the voltage on said first error input node for driving a voltage onto said first error input line, said means responsive to the voltage on said second input signal node for driving a voltage onto said second signal input line, and said means responsive to the voltage on said second error signal node for driving a voltage onto said second error input line. comprise buffer amplifiers.

34. A continuous learning system comprising:

an array of synaptic elements arranged in rows and columns on the surface of an integrated circuit,

an input signal associated with each row of said array,

an error signal associated with each column of said array,

input conductors aligned with the rows of said synaptic elements,

error conductors aligned with the columns of said synaptic elements,

driving means for encoding said input signals into voltages on said input conductors,

driving means for encoding said error signals into voltages on said error conductors,

each synaptic element comprising;

a single floating node,

electron tunneling means, connected to said floating node, for tunneling electrons from said floating node,

hot electron injection means, connected to said floating node, for injecting electrons onto said floating node,

control means, responsive to the voltages on the input conductors associated with the row in which said synaptic element is located, and to the voltages on the error conductors associated with the column in which said synaptic element is located, for activating said electron tunneling means when the product of the error signal and the input signal is of a first sign, and for activating said hot electron injection means when the product of the error signal and the input signal is of a second sign, opposite to said first sign.