Protocol processing apparatus for use in interfacing network connected computer systems utilizing separate paths for control information and data transfer

• US 5,303,344 A
• Filed: 02/25/1991
• Issued: 04/12/1994
• Est. Priority Date: 03/13/1989
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hirata, Tetsuhiko, Mizutani, Mika, Yokoyama, Tatsuya, Matsui, Susumu, Terada, Matsuaki
• Primary Examiner(s): Kulik, Paul V.
• Assistant Examiner(s): Amsbury, Wayne
• Application Number:
  US07/659,705
• Time in Patent Office: 1,142 Days
• Field of Search: 395/200, 364/900, 364/DIG. 1, 370/95.1
• US Class Current: 709/230
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A communication control equipment connected between a computer and a network so as to perform protocol processing at a high speed, has a buffer memory connected between a computer interface circuit and a network interface circuit through a first path for data transfer, so as to temporarily store communication data, and a protocol processor connected between the computer interface circuit and the network interface circuit through a second path for control information transfer. The protocol processor is also connected to the buffer memory through a third path so as to effect protocol processing on the communication data within the buffer memory. The protocol processor includes a plurality of processor units connected in series in the second path so as to respond to control information received from the second path to make access to the buffer memory through the third path and to execute a first category of protocol processing necessary in normal data transfer on the communication data stored in the buffer memory. If protocol processing other than the first category of protocol processing on the communication data is necessary, the processor units supply the control information to the third path. The protocol processing also includes a second processor which operates as a backend processor for the processor units and which is connected to the third path so as to respond to the control information received from the third path to execute protocol processing other than the first category of protocol processing on the communication data stored in the buffer memory.

Claims

1. A communication control equipment connected between a computer system and a network, comprising:

computer interface means, connected to said computer system, for communicating with said computer system;

network interface means, connected to said network, for communicating with said network;

buffer memory means, connected between said computer interface means and said network interface means through a first path for data transfer, for temporarily storing protocol data in association with communication data to be transmitted from said network interface means or received by said computer system; and

protocol processor means for performing protocol processing on said protocol data within said buffer memory, said protocol processor means being connected between said computer interface means and said network interface means through a second path for control information transfer and being connected to said buffer memory means through a third path to access said buffer memory means;

said protocol processor means comprising;

first processor means, connected to said second and third paths, for accessing said buffer memory means in response to said control information transferred through said second path, for executing a first category of protocol processing, necessary for normal data transfer of said communication data, on said protocol data stored in said buffer memory means, and for transferring said control information to said third path if protocol processing other than said first category of protocol processing is necessary for said protocol data; and

second processor means, connected to said third path, for accessing said buffer memory means in response to said control information received through said third path, and for executing protocol processing other than said first category of protocol processing on said protocol data stored in said buffer memory means;

wherein said network interface means includes means for reading out said communication data and said processed protocol data from said buffer memory means and for transmitting the communication data to said network in a predetermined format in response to the reception of control information for data transmission from said second path, and means for writing new communication data in association with new protocol data into said buffer memory means and for issuing new control information for data reception to said second path when the communication data is received in a predetermined format from said network.

2. A communication control equipment according to claim 1, wherein said protocol has a structure of a plurality of layers, and said first processor means comprises a plurality of processor units connected in series in said second path so as to execute protocol processing of different layers.

3. A communication control equipment according to claim 2, wherein said second path comprises:

a first control bus for transferring control information for data transmission in a first direction from said computer interface means to said network interface means; and

a second control bus for transferring control information for data reception in a second direction from said network interface means to said computer interface means, and wherein each of said processor units is connected to each of said first and second control buses through first-in, first-out buffers, respectively.

4. A communication control equipment according to claim 2, wherein said buffer memory means comprises:

a buffer region for storing said communication data and said protocol data; and

a control region for storing a plurality of command descriptors provided in correspondence to said communication data, respectively;

each of said command descriptors being formed of a plurality of entries corresponding to said plurality of layers, each of said entries including a command code, a connection identifier and a buffer address for indicating the location of the communication data or the protocol data in said buffer region in association with the connection identifier;

said control information including address information for specifying one of said command descriptors, and

each of said processor units operating in accordance with said control information to access on of the entries which is within the command descriptor specified by the control information and corresponds to the protocol layer related to the processor unit, thereby executing protocol processing operation for the entry.

5. A communication control equipment according to claim 4, wherein said second path comprises:

a first control bus for transferring control information in a direction from said computer interface means to said network interface means; and

a second control bus for transferring said control information in a direction from said network interface means to said computer interface means; and

each of said processor units comprises;

a first set of first-in, first-out buffers connected to said first control bus so as to receive control information from the upstream side of the first control bus and to transmit control information to the downstream side of the first control bus, respectively, and

a second set of first-in, first-out buffers connected to said second control bus so as to receive control information from the upstream side of the second control bus and to transmit control information to the downstream side of the second control bus, respectively; and

means for making access to said command descriptor in said buffer memory means on the basis of the control information read out from said first-in, first-out buffers connected to the upstream side of said first and second control buses and for making access to said buffer region on the basis of the contents of the command descriptor.

6. A communication control equipment connected between a computer system and a network, comprising:

computer interface means, connected to said computer system, for communicating with said computer system;

network interface means, connected to said network, for communicating with said network;

buffer memory means, connected between said computer interface means and said network interface means through a first path for data transfer, for temporarily storing protocol data in association with communication data to be transmitted from said network interface means or received by said computer system; and

protocol processor means for performing protocol processing on said protocol data within said buffer memory, said protocol processor means being connected between said computer interface means and said network interface means through a second path for control information transfer and connected to said buffer memory means through a third path to access said buffer memory means;

said protocol processor means comprising;

an internal bus connected to said third path;

first processor means, connected to said internal bus and said second path, for accessing said buffer memory means in response to said control information received from said second path, for executing a first category of protocol processing necessary for normal data transfer of said communication data on said protocol data stored in said buffer memory means and for transferring said control information to said internal bus if protocol processing other than said first category of protocol processing is necessary for said protocol data; and

second processor means, connected to said internal bus, for accessing said buffer memory means in response to said control information received from said first processor means through said internal bus, for executing protocol processing other than said first category of protocol processing on said protocol data stored in said buffer memory means and for supplying said control information to said first processor means through said internal bus;

wherein said network interface means includes means for reading out said communication data and said processed protocol data from said buffer memory means and for transmitting the communication data to said network in a predetermined format in response to the control information for data transmission from said second path, and means for writing new communication data in association with new protocol data into said buffer memory means and for issuing new control information for data reception to said second path when the communication data is received in a predetermined format from said network.

7. A communication control equipment according to claim 6, wherein said protocol has a structure of a plurality of layers, and said first processor means comprises a plurality of processor units connected in series by said second path so as to execute protocol processing for different layers.

8. A communication control equipment according to claim 7, wherein said second path comprises:

a first control bus for transferring control information as to data transmission in a first direction from said computer interface means to said network interface means; and

a second control bus for transferring said control information as to data reception in a second direction from said network interface means to said computer interface means; and

wherein each of said processor units is connected to each of said first and second control buses through first-in, first-out buffers, respectively.

9. A communication control equipment according to claim 8, wherein said buffer memory means comprises:

a buffer region for storing said communication data and said protocol data; and

a control region for storing a plurality of command descriptors provided in correspondence to said communication data, respectively;

each of said command descriptors being formed of a plurality of entries corresponding to a plurality of layers and each including a command code, a connection identifier, a data length and a buffer address for indicating the location of the communication data or the protocol data in said buffer region in association with the connection identifier;

said control information including address information for specifying one of said command descriptors; and

each of said processor units operating in accordance with said control information to access one of the entries, which is within the command descriptor specified by the control information and corresponds to the protocol layer related to the processor unit, thereby performing protocol processing operation for the entry.

10. A communication control equipment according to claim 9, wherein said second path comprises:

a first control bus for transferring control information in a direction from said computer interface means to said network interface means; and

a second control bus for transferring said control information in a direction from said network interface means to said computer interface means; and

each of said processor units comprises;

a first set of first-in, first-out buffers connected to said first control bus so as to receive control information from the upstream side of the first control bus and to transmit control information to the downstream side of the first control bus, respectively; and

a second set of first-in, first-out buffers connected to said second control bus so as to receive control information from the upstream side of the second control bus and to transmit control information to the downstream side of the second control bus, respectively; and

means for making access to said command descriptor in said buffer memory means on the basis of the control information read out from said first-in, first-out buffers connected to the upstream side of said first and second control buses and for making access to said buffer region on the basis of the contents of the command descriptor being accessed.

11. A communication control equipment according to claim 6, wherein:

said buffer memory comprises a plurality of sub-memories accessible in one byte units and connected in parallel to said internal bus; and

a boundary controller between said buffer memory and said internal bus for incrementing a memory address on said internal bus to generate a second address, and for supplying said second address to at least one of said plurality of sub-memories when one unit of data to be read out from or written into said buffer memory exceeds the capacity of a memory region which can be accessed by one memory address that is supplied from said first or second processor to said internal bus.

12. A communication control equipment connected between a computer system and a network, comprising:

computer interface means, connected to said computer system, for communicating with said computer system;

network interface means, connected to said network for communicating with said network;

buffer memory means, connected between said computer interface means and said network interface means through a first path for data transfer, for temporarily storing protocol data in association with communication data to be transmitted from said network interface means or received by said computer system; and

protocol processor means for performing protocol processing on said protocol data within said buffer memory, said protocol processor means being connected between said computer interface means and said network interface means through a second path for control information transfer and connected to said buffer memory means through a third path to access said buffer memory means;

said protocol processor means comprising;

a first internal bus connected to said third path;

first processor means, connected to said first internal bus and second path, for accessing said buffer memory means in response to said control information received from said second path, for executing a first category of protocol processing necessary for normal data transfer of said communication data on said protocol data stored in said buffer memory means, and for transferring said control information to a second internal bus if protocol processing other than said first category of protocol processing is necessary for said protocol data; and

second processor means, connected to said first and second internal buses, for accessing said buffer memory means through said second internal bus in response to said control information received from said first processor means through said first internal bus, for executing protocol processing other than said first category for protocol processing on said protocol data stored in said buffer memory means, and then for supplying said control information to said first processor means through said second internal bus;

wherein said network interface means includes means for reading out said communication data and said processed protocol data from said buffer memory means and for transmitting the communication data to said network in a predetermined format in response to the control information for data transmission from said second path, and means for writing new communication data in association with new protocol data into said buffer memory means and for issuing new control information for data reception to said second path when the communication data is received in a predetermined format from said network.

13. A communication control equipment according to claim 12, wherein said protocol has a structure of a plurality of layers, and said first processor means comprises a plurality of processor units connected in parallel between said first and second internal buses and connected in series by said second path so as to execute protocol processing for different layers.

14. A communication control equipment according to claim 13, wherein said second path comprises:

a first control bus for transferring control information in a first direction from said computer interface means to said network interface means; and

a second control bus for transferring control information in a second direction from said network interface means to said computer interface means; and

wherein each of said processor units is connected to each of first and second control buses through first-in, first-out buffers, respectively.

15. A communication control equipment connected between a computer system and a network, comprising:

computer interface means, connected to said computer system, for communicating with said computer system;

network interface means, connected to said network, for communicating with said network;

buffer memory means, connected between said computer interface means and said network interface means through a first path for data transfer, for temporarily storing protocol data in association with communication data to be transmitted from said network interface means or received by said computer system; and

protocol processor means for performing protocol processing on said protocol data within said buffer memory, said protocol processor means being connected between said computer interface means and said network interface means through a second path for control information transfer and connected to said buffer memory means through a third path to access said buffer memory means;

said protocol processor means comprising;

an internal bus connected to said third path;

a plurality of first processors, each provided for a different protocol layer and being connected in series in said second path and in parallel to said internal bus so as to access said buffer memory means in response to control information received from said second path through said internal bus, for executing a first category of protocol processing necessary for normal data transfer of said communication data on said protocol data stored in said buffer memory means; and

a plurality of second processors provided in correspondence to respective ones of said protocol layers and being connected to said plurality of first processors through internal signal lines and to said buffer memory through said internal bus, respectively;

each of said first processors supplying control information to one of said internal signal lines connected thereto if protocol processing other than said first category of protocol processing is necessary on said protocol data;

each of said second processors including means responsive to control information received from said first processor through said internal signal line to make access to said buffer memory means through said internal bus, to execute protocol processing other than said first category of protocol processing on the protocol data stored in said first buffer memory means, and then to supply the control information through said internal signal line to a first processor;

wherein said network interface means includes means for reading out said communication data and said processed protocol data from said buffer memory means and for transmitting the communication data to said network in a predetermined format in response to the control information for data transmission from said second path, and means for writing new communication data in association with new protocol data into said buffer memory means and for issuing new control information for data reception to said second path when the communication data is received in a predetermined format from said network.

16. A high speed protocol apparatus connected between said computer interface means for connecting with a computer system and network interface means for connecting with a network so as to make access to buffer memory means, which is connected between said computer interface means and said network interface means for temporarily storing communication data and protocol data, and to execute processing of a layered protocol on the protocol data associated with the communication data at a high speed, comprising:

control information path means for transferring control information between said computer interface means and said network interface means;

an internal bus connected to said buffer memory means;

at least one first processor, connected said internal bus and said control information path means so as to receive control information from said control information path mans and to make access to said buffer memory means through said internal bus, for executing a first category of protocol processing necessary for normal data transfer on the protocol data stored in said buffer memory means in accordance with said received control information; and

a second processor, connected to said internal bus, for executing protocol processing other than said first category of protocol processing;

said first processor including means for supplying the control information to said internal signal bus if protocol processing other than said first category of protocol processing is necessary on said protocol data,

said second processor including means responsive to the control information received from said first processor through said internal bus for accessing said buffer memory means through said internal bus to execute protocol processing other than said first category of protocol processing on the protocol data stored in said buffer memory, and then to supply the control information to said first processor through said internal bus.

17. A high speed protocol processing apparatus according to claim 16, wherein said control information path means comprises information paths each having a signal transmission direction opposite to each other, and said first processor is connected to said control information paths through first-in, first-out buffers.

18. A high speed protocol processing apparatus according to claim 16, wherein said first processor comprises a plurality of processor units each provided in correspondence to a respective layer of communication protocol and connected in series by said control information path means formed of a pair of information paths each having a transmission direction opposite to each other, so as to be independently operable.

19. A high speed protocol processing apparatus according to claim 18, wherein each of said processor units has a plurality of first-in, first-out buffers serving as connection interfaces for communicating control information with information paths.

20. A high speed protocol processing apparatus according to claim 18, wherein each of said processor units comprises:

a first circuit for reading and writing a protocol header as part of the protocol data from and in said buffer memory means;

a second circuit for analyzing a protocol header of communication data when the communication data stored in said buffer memory means and to be processed in protocol is the data received from the network;

a decision circuit for deciding whether or not the communication data to be processed in protocol belongs to a normal data transfer operation;

register means for storing various information necessary for the execution of protocol processing;

a third circuit for executing protocol processing on protocol data read out from said buffer memory means in response to a decision signal from said decision circuit;

a fourth circuit for generating a protocol header of transmission data to be stored as a part of the protocol data in said buffer memory means in a normal data transfer operation; and

a control circuit for controlling the operation of said first through fourth circuits.

21. A high speed protocol processing apparatus according to claim 16, further comprising a flag register, provided between said first processor and said second processor, for supplying flag information to said first processor to notify said first processor that said second processor has finished the protocol processing associated with said control information after the control information is supplied from said first processor to said second processor through said internal bus.

22. A high speed protocol processing apparatus according to claim 21, wherein said first processor includes a register accessible from said second processor so that said second processor can inform said first processor, by setting flag information in the register, whether or not a data transfer is possible through the network due to the establishment of a connection between two systems which are to make communication with each other.