Reentrant protected mode kernel using virtual 8086 mode interrupt service routines

• US 5,303,378 A
• Filed: 05/21/1991
• Issued: 04/12/1994
• Est. Priority Date: 05/21/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Cohen, Leonardo
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): BUTLER, DENNIS
• Application Number:
  US07/703,499
• Time in Patent Office: 1,057 Days
• Field of Search: 395/425, 395/650, 395/700, 395/400, 364/200, 364/900
• US Class Current: 710/264
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings

Abstract

A method for allowing a protected mode kernel to service, in virtual 8086 mode, hardware interrupts which occur during execution of ring 0 protected mode code. When an interrupt occurs during execution of ring 0 code, the microprocessor copies the state of the last virtual 8086 environment on the top of the ring 0 stack and modifies this state to begin execution of the appropriate interrupt service routine in virtual 8086 mode. The kernel utilizes a secondary stack to keep track of the last virtual 8086 environment saved on the ring 0 stack and updates the ring 0 stack pointer in the respective task'"'"'s task state segment to the new beginning of the ring 0 stack each time a ring transition occurs from ring 3 V86 mode to ring 0 protected mode. By manipulating the ring 0 stack and utilizing the secondary stack to keep track of interrupted V86 environments, the kernel can allow interrupts to be nested down multiple levels.

Claims

1. A method for servicing exceptional conditions in a computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task state information, the computer system having a secondary stack and a pointer which points to the top of the second privilege level stack, the method comprising:

(a) transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) retrieving the second privilege level stack top pointer after transitioning from the first privilege level to the second privilege level;

(c) placing the first privilege level task state information on top of the second privilege level stack after retrieving the second privilege level stack top pointer;

(d) placing a pointer to the first privilege level task state information on the secondary stack after placing the first privilege level task state information on the second privilege level stack;

(e) enabling interrupts and executing the second privilege level task after placing said first privilege level task state information pointer on the secondary stack;

(f) placing the second privilege level task state information on the second privilege level stack after an occurrence of an exceptional condition after enabling interrupts and beginning execution of the second privilege level task;

(g) executing an exception handler after placing said second privilege level task state information if said exceptional condition is an exception and returning to execution of said second privilege level task in step (e) after completion of said exception handler;

(h) saving certain data register values on the second privilege level stack after placing said second privilege level task state information if said exceptional condition is a hardware interrupt;

(i) retrieving the most recent first privilege level task state information pointer from the secondary stack after saving said certain data register values;

(j) copying the first privilege level task state information indicated by said most recent first privilege level task state information pointer to the top of the second privilege level stack after retrieving said most recent first privilege level task state information pointer;

(k) determining the entry address of an interrupt service routine required to handle said hardware interrupt after saving said certain data register values;

(l) modifying said copied first privilege level task state information to indicate execution at said entry address of said interrupt service routine after determining said entry address and copying said first privilege level task state information;

(m) modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task state information after modifying said copied first privilege level task state information;

(n) beginning execution of said interrupt service routine at the first privilege level and removing said copied and modified first privilege level task state information from the second privilege level stack after modifying the second privilege level stack top pointer;

(o) executing said first privilege level interrupt service routine after beginning execution, during which execution interrupts may be enabled, whereupon an exceptional condition occurring requesting a second privilege level task causes steps (a) through (e) to be repeated;

(p) returning to the second privilege level after said interrupt service routine completes;

(q) modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(r) retrieving the second privilege level task state information from the second privilege level stack after returning to the second privilege level;

(s) returning execution to the second privilege level task after retrieving the second privilege level task state information, whereupon an exceptional condition occurring causes steps (f) through (o) to be repeated;

(t) retrieving the most recent pointer from the top of the secondary stack upon completion of the second privilege level task; and

(u) returning to the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said pointer retrieved from the secondary stack in step (t) upon completion of the second privilege level task.

3. The method of claims 1 or 2, further comprising:

appending a value to the first privilege level stack after saving said data register values in step (h),

wherein said value causes execution to proceed to an end of interrupt routine which causes entry into the second privilege level when said value is popped off of the first privilege level stack, and

wherein said value is popped off of the first privilege level stack to return to the second privilege level in step (p).

4. The method of claim 3, wherein said returning to the second privilege level in step (p) places first privilege level task state information on the second privilege level stack, the method further comprising:

discarding said first privilege level task state information created by said returning to the second privilege level in step (p) after returning to the second privilege level.

5. The method of claims 1 or 2, wherein the second privilege level has a greater privilege than the first privilege level.

6. The method of claims 1 or 2, wherein the first privilege level task is executing prior to step (a), and

wherein said transitioning from the first privilege level to the second privilege level in step (a) is caused by an exceptional condition requesting the second privilege level task.

2. A method for servicing exceptional conditions in a computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task state information, the computer system having memory, a secondary stack, a pointer which points to the top of the second privilege level stack, and a programmable interrupt controller which includes an in-service register indicating the current hardware interrupt being serviced, wherein the computer system maintains a virtual copy of the in-service register in the memory, the method comprising:

(a) transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) retrieving the second privilege level stack top pointer after transitioning from the first privilege level to the second privilege level;

(c) placing the first privilege level task state information on top of the second privilege level stack after retrieving the second privilege level stack top pointer;

(d) placing a pointer to the first privilege level task state information on the secondary stack after placing the first privilege level task state information on the second privilege level stack;

(e) enabling interrupts and executing the second privilege level task after placing said first privilege level task state information pointer on the secondary stack;

(f) placing the second privilege level task state information on the second privilege level stack after an occurrence of an exceptional condition after enabling interrupts and beginning execution of the second privilege level task;

(g) checking the status of the in-service register virtual copy after placing said second privilege level task state information to determine if said exceptional condition is a hardware interrupt;

(h) saving certain data register values on the second privilege level stack if said exceptional condition is a hardware interrupt as determined in step (g);

(i) retrieving the most recent first privilege level task state information pointer from the secondary stack after saving said certain data register values;

(j) copying the first privilege level task state information indicated by said most recent first privilege level task state information pointer to the top of the second privilege level stack after retrieving said most recent first privilege level task state information pointer;

(k) determining the entry address of an interrupt service routine required to handle said hardware interrupt after saving said certain data register values;

(l) modifying said copied first privilege level task state information to indicate execution at said entry address of said interrupt service routine after determining said entry address and copying said first privilege level task state information;

(m) modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task state information after modifying said copied first privilege level task state information;

(n) beginning execution of said interrupt service routine at the first privilege level and removing said copied and modified first privilege level task state information from the second privilege level stack after modifying the second privilege level stack top pointer;

(o) executing said first privilege level interrupt service routine after beginning execution, during which execution interrupts may be enabled, whereupon an exceptional condition occurring requesting a second privilege level task causes steps (a) through (e) to be repeated;

(p) returning to the second privilege level after said interrupt service routine completes;

(q) modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(r) retrieving the second privilege level task state information from the second privilege level stack after returning to the second privilege level;

(s) returning execution to the second privilege level task after retrieving the second privilege level task state information, whereupon an exceptional condition occurring causes steps (f) through (o) to be repeated;

(t) retrieving the most recent pointer from the top of the secondary stack upon completion of the second privilege level task; and

(u) returning to the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said pointer retrieved from the secondary stack in step (t) upon completion of the second privilege level task.

7. A method for servicing exceptional conditions in a computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task information, the computer system including a secondary stack and a pointer which points to the top of the second privilege level stack, the method comprising:

(a) transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) retrieving the second privilege level stack top pointer after transitioning from the first privilege level to the second privilege level;

(c) placing the first privilege level task information on the top of the second privilege level stack after retrieving the second privilege level stack top pointer;

(d) placing a pointer to the first privilege level task information on the secondary stack after placing the first privilege level task information on the second privilege level stack;

(e) enabling interrupts and executing the second privilege level task after placing said first privilege level task information pointer on the secondary stack;

(f) placing the second privilege level task information on the second privilege level stack after an occurrence of an exceptional condition after enabling interrupts and beginning execution of the second privilege level task;

(g) executing an exception handler after placing said second privilege level task state information if said exceptional condition is an exception and returning to execution of said second privilege level task in step (e) after completion of said exception handler;

(h) saving certain data register values on the second privilege level stack after placing said second privilege level task state information if said exceptional condition is a hardware interrupt;

(i) retrieving the most recent first privilege level task information pointer from the secondary stack after saving said certain data register values;

(j) copying the first privilege level task information indicated by said most recent first privilege level task information pointer to the top of the second privilege level stack after retrieving said most recent first privilege level task information pointer;

(k) determining the entry address of an interrupt service routine required to handle said hardware interrupt after saving said certain data register values;

(l) modifying said copied first privilege level task information to indicate execution at said entry address of said interrupt service routine after determining said entry address and copying said first privilege level task information;

(m) modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task information after modifying said copied first privilege level task information;

(n) appending a value to the first privilege level stack after occurrence of said exceptional condition, wherein said value causes execution to proceed to an end of interrupt routine which causes entry into the second privilege level and placement of end of interrupt routine task information on the second privilege level stack when said value is popped off of the first privilege level stack;

(o) beginning execution of said interrupt service routine at the first privilege level and removing said copied and modified first privilege level task information from the second privilege level stack after modifying the second privilege level stack top pointer and appending said value to the first privilege level stack;

(p) executing said first privilege level interrupt service routine after beginning execution, during which execution interrupts may be enabled, whereupon an exceptional condition occurring which requests a second privilege level task causes steps (a) through (e) to be repeated;

(q) popping said value off of the first privilege level stack to execute said end of interrupt routine and return to the second privilege level upon completion of said first privilege level interrupt service routine;

(r) discarding said end of interrupt routine task information placed on the second privilege level stack by said entry to the second privilege level after returning to the second privilege level;

(s) modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(t) restoring said saved certain second privilege level register values from the second privilege level stack after returning to the second privilege level;

(u) returning execution of the second privilege level task using the second privilege level task information placed on the second privilege level stack after restoring said saved certain second privilege level register values, whereupon an exceptional condition occurring causes steps (f) through (p) to be repeated;

(v) retrieving the most recent pointer from the top of the secondary stack upon completion of the second privilege level task; and

(w) returning to the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said pointer retrieved from the secondary stack in step (v) upon completion of the second privilege level task.

9. The method of claims 7 or 8, wherein the second privilege level has a greater privilege than the first privilege level.

10. The method of claims 7 or 8, wherein said exceptional condition of step (p) which causes said transitioning from the first privilege level to the second privilege level is a software interrupt requesting a protected mode service.

8. A method for servicing exceptional conditions in a computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task information, the computer system having memory, a secondary stack, a pointer which points to the top of the second privilege level stack, and a programmable interrupt controller which includes an in-service register indicating the current hardware interrupt being serviced, wherein the computer system maintains a virtual copy of the in-service register in the memory, the method comprising:

(a) transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) retrieving the second privilege level stack top pointer after transitioning from the first privilege level to the second privilege level;

(c) placing the first privilege level task information on the top of the second privilege level stack after retrieving the second privilege level stack top pointer;

(d) placing a pointer to the first privilege level task information on the secondary stack after placing the first privilege level task information on the second privilege level stack;

(e) enabling interrupts and executing the second privilege level task after placing said first privilege level task information pointer on the secondary stack;

(f) placing the second privilege level task information on the second privilege level stack after an occurrence of an exceptional condition after enabling interrupts and beginning execution of the second privilege level task;

(g) checking the status of the in-service register virtual copy after placing said second privilege level task state information to determine if said exceptional condition is a hardware interrupt;

(h) saving certain data register values on the second privilege level stack if said exceptional condition is a hardware interrupt as determined in step (g);

(i) retrieving the most recent first privilege level task information pointer from the secondary stack after saving said certain data register values;

(j) copying the first privilege level task information indicated by said most recent first privilege level task information pointer to the top of the second privilege level stack after retrieving said most recent first privilege level task information pointer;

(k) determining the entry address of an interrupt service routine required to handle said hardware interrupt after saving said certain data register values;

(l) modifying said copied first privilege level task information to indicate execution at said entry address of said interrupt service routine after determining said entry address and copying said first privilege level task information;

(m) modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task information after modifying said copied first privilege level task information;

(n) appending a value to the first privilege level stack after occurrence of said exceptional condition, wherein said value causes execution to proceed to an end of interrupt routine which causes entry into the second privilege level and placement of end of interrupt routine task information on the second privilege level stack when said value is popped off of the first privilege level stack;

(o) beginning execution of said interrupt service routine at the first privilege level and removing said copied and modified first privilege level task information from the second privilege level stack after modifying the second privilege level stack top pointer and appending said value to the first privilege level stack;

(p) executing said first privilege level interrupt service routine after beginning execution, during which execution interrupts may be enabled, whereupon an exceptional condition occurring which requests a second privilege level task causes steps (a) through (e) to be repeated;

(q) popping said value off of the first privilege level stack to execute said end of interrupt routine and return to the second privilege level upon completion of said first privilege level interrupt service routine;

(r) discarding said end of interrupt routine task information placed on the second privilege level stack by said entry to the second privilege level after returning to the second privilege level;

(s) modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(t) restoring said saved certain second privilege level register values from the second privilege level stack after returning to the second privilege level;

(u) returning execution to the second privilege level task using the second privilege level task information placed on the second privilege level stack after restoring said saved certain second privilege level register values, whereupon an exceptional condition occurring causes steps (f) through (p) to be repeated;

(v) retrieving the most recent pointer from the top of the secondary stack upon completion of the second privilege level task; and

(w) returning to the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said pointer retrieved from the secondary stack in step (v) upon completion of the second privilege level task.

11. A computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task state information, the computer system including a secondary stack and a pointer which points to the top of the second privilege level stack, the computer system comprising:

(a) means for transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) means for placing the first privilege level task state information on the top of the second privilege level stack utilizing the second privilege level stack top pointer;

(c) means for placing a pointer to the first privilege level task state information on the secondary stack after placement of said first privilege level task state information;

(d) means for enabling interrupts and executing the second privilege level task after placement of said first privilege level task state information pointer on the secondary stack;

(e) means for placing the second privilege level task state information on the second privilege level stack after an occurrence of an exceptional condition during execution of the second privilege level task;

(f) means for invoking an exception handler routine after placement of said second privilege level task state information if said exceptional condition is an exception;

(ff) means for returning to execution of said second privilege level task upon completion of said exception handler routine;

(g) means for saving certain data register values on the second privilege level stack after placement of said second privilege level task state information if said exceptional condition is a hardware interrupt;

(h) means for copying the first privilege level task state information indicated by said first privilege level task state information pointer to the top of the second privilege level stack after the saving of said certain data register values;

(i) means for determining the entry address of an interrupt service routine required to handle said hardware interrupt after the saving of said certain data register values;

(j) means for modifying said copied first privilege level task state information to indicate execution at said entry address of said interrupt service routine after the determination of said entry address and the copying of said first privilege level task state information;

(k) means for modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task state information after modifying said copied first privilege level task state information;

(l) means for beginning execution of said interrupt service routine at the first privilege level, and for removing said copied and modified first privilege level task state information from the second privilege level stack;

(m) means for enabling interrupts during said interrupt service routine, whereupon an exceptional condition occurring requesting a second privilege level task causes said means (a) through (d) to operate;

(n) means for returning to the second privilege level upon completion of said first privilege level interrupt service routine;

(o) means for modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(oo) means for retrieving the second privilege level task state information from the second privilege level stack after returning to the second privilege level;

(p) means for returning the microprocessor to execution of the second privilege level task using the second privilege level task state information saved on the second privilege level stack, whereupon an exceptional condition occurring requesting a first privilege level interrupt service routine causes said means (e) through (m) to operate;

(q) means for retrieving the most recent pointer from the top of the secondary stack upon completion of said second privilege level task; and

(r) means for returning the microprocessor to execution of the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said most recent pointer retrieved from the secondary stack.

13. The computer systems of claims 11 or 12, further comprising:

means for appending a value to the first privilege level stack after operation of said certain data register value placing means (g),

wherein said value causes execution to proceed to an end of interrupt routine which causes entry into the second privilege level when said value is popped off of the first privilege level stack, and

said second privilege level returning means (n) pops said value off of the first privilege level stack to return to the second privilege level.

14. The computer system of claims 13, wherein said second privilege level returning means (n) places first privilege level task state information on the second privilege level stack, the computer system further comprising:

means for discarding said first privilege level task state information placed on said second privilege level stack by said returning means.

12. A computer system utilizing a microprocessor having data registers, a first privilege level and a second privilege level, each privilege level having an associated stack, the microprocessor executing tasks operating at each privilege level having respective task state information, the computer system including memory, a secondary stack, a pointer which points to the top of the second privilege level stack, and a programmable interrupt controller which includes an in-service register indicating the current hardware interrupt being serviced, the computer system comprising:

(aa) means for maintaining a virtual copy of the in-service register in the memory;

(a) means for transitioning from the first privilege level to the second privilege level to execute the second privilege level task;

(b) means for placing the first privilege level task state information on the top of the second privilege level stack utilizing the second privilege level stack top pointer;

(c) means for placing a pointer to the first privilege level task state information on the secondary stack after placement of said first privilege level task state information;

(d) means for enabling interrupts and executing the second privilege level task after placement of said first privilege level task state information pointer on the secondary stack;

(e) means for placing the second privilege level task state information on the second privilege level stack after an occurrence of an exceptional condition during execution of the second privilege level task;

(f) means for determining after the placement of said second privilege level task state information if said exceptional condition is a hardware interrupt by checking the status of the in-service register virtual copy;

(g) means for saving certain data register values on the second privilege level stack if said exceptional condition is a hardware interrupt;

(h) means for copying the first privilege level task state information indicated by said first privilege level task state information pointer to the top of the second privilege level stack after the saving of said certain data register values;

(i) means for determining the entry address of an interrupt service routine required to handle said hardware interrupt after the saving of said certain data register values;

(j) means for modifying said copied first privilege level task state information to indicate execution at said entry address of said interrupt service routine after the determination of said entry address and the copying of said first privilege level task state information;

(k) means for modifying the second privilege level stack top pointer to point to said copied and modified first privilege level task state information after modifying said copied first privilege level task state information;

(l) means for beginning execution of said interrupt service routine at the first privilege level and for removing said copied and modified first privilege level task state information from the second privilege level stack;

(m) means for enabling interrupts during said interrupt service routine, whereupon an exceptional condition occurring requesting a second privilege level task causes said means (a) through (d) to operate;

(n) means for returning to the second privilege level upon completion of said first privilege level interrupt service routine;

(o) means for modifying the second privilege level stack top pointer to the pointer value most recently placed on the secondary stack after returning to the second privilege level;

(oo) means for retrieving the second privilege level task state information from the second privilege level stack after returning to the second privilege level;

(p) means for returning the microprocessor to execution of the second privilege level task using the second privilege level task state information saved on the second privilege level stack, whereupon an exceptional condition occurring requesting a first privilege level interrupt service routine causes said means (e) through (m) to operate;

(q) means for retrieving the most recent pointer from the top of the secondary stack upon completion of said second privilege level task; and

(r) means for returning the microprocessor to execution of the first privilege level task or interrupt service routine using the first privilege level task state information on the second privilege level stack pointed to by said most recent pointer retrieved from the secondary stack.

15. A method for allowing an operating system kernel to service exceptional conditions in virtual 8086 mode during execution of ring 0 code in a computer system having an 80386-compatible microprocessor which includes a virtual 8086 mode and a protected mode of operation, a high privilege level referred to as ring 0 which has associated with it a ring 0 stack, a low privilege level referred to as ring 3 which has associated with it a ring 3 stack, and data registers, the computer system further including a secondary stack and memory which includes a virtual 8086 task operating at ring 3 level and a task state segment associated with the task which includes a ring 0 stack pointer that points to the beginning of the ring 0 stack, the ring 0 code and the virtual 8086 task each having an associated task state, the method comprising:

(a) transitioning from virtual 8086 mode to protected mode to execute the ring 0 code;

(b) retrieving the ring 0 stack pointer after transitioning from virtual 8086 mode to protected mode;

(c) placing the virtual 8086 task state on the ring 0 stack after retrieving the ring 0 stack pointer;

(d) pushing a pointer to said virtual 8086 task state on the secondary stack after placing said virtual 8086 task state;

(e) enabling interrupts and beginning execution of said ring 0 code after pushing said pointer;

(f) saving the ring 0 code task state on the ring 0 stack after occurrence of an exceptional condition after enabling interrupts and beginning execution;

(g) executing an exception handler after saving the ring 0 code task state if said exceptional condition is an exception and returning to execution of said ring 0 code in step (e) after completion of said exception handler;

(h) saving current data register values on the ring 0 stack after saving the ring 0 code task state if said exceptional condition is a hardware interrupt;

(i) retrieving the most recent virtual 8086 task state pointer on the secondary stack after saving said data register values;

(j) copying the virtual 8086 task state pointed to by said most recent virtual 8086 task state pointer on the top of the ring 0 stack after retrieving said most recent virtual 8086 task state pointer;

(k) determining the entry address of an interrupt service routine required to service said hardware interrupt after occurrence of said exceptional condition;

(l) modifying said copied virtual 8086 task state to indicate execution at said interrupt service routine entry address after determining said entry address;

(m) modifying the ring 0 stack pointer to point to said copied and modified virtual 8086 task state on the ring 0 stack after copying said virtual 8086 task state;

(n) appending a pointer to the ring 3 stack after occurrence of said exceptional condition, wherein said ring 3 stack pointer causes execution to proceed to an end of interrupt routine that traps back to protected mode and further causes end of interrupt routine task information to be placed on the ring 0 stack;

(o) entering virtual 8086 mode and beginning execution of said interrupt service routine after appending said pointer;

(p) executing the interrupt service routine, during which time interrupts may be enabled, wherein an exceptional condition occurring during said interrupt service routine causes steps (a) through (e) to be repeated;

(q) popping said ring 3 stack pointer off of the ring 3 stack to execute said end of interrupt routine and return to protected mode after completion of said interrupt service routine;

(r) discarding said end of interrupt routine task information placed on the ring 0 stack by said entry to protected mode after returning to protected mode;

(s) modifying the ring 0 stack pointer to the pointer value most recently placed on the secondary stack after returning to protected mode;

(t) restoring said saved data register values from the ring 0 stack after returning to protected mode;

(u) returning execution to the ring 0 code using the ring 0 task state on the ring 0 stack after restoring said saved data register values, wherein an exceptional condition would cause steps (f) through (p) to be repeated;

(v) retrieving the most recent pointer from the top of the secondary stack upon completion of the ring 0 code; and

(w) returning to the virtual 8086 mode task or interrupt service routine using the virtual 8086 task state information on the ring 0 stack pointed to by said most recent pointer retrieved from the secondary stack in step (v) after completion of the ring 0 code.

16. A method for allowing an operating system kernel to service exceptional conditions in virtual 8086 mode during execution of ring 0 code in a computer system having an 80386-compatible microprocessor which includes a virtual 8086 mode and a protected mode of operation, a high privilege level referred to as ring 0 which has associated with it a ring 0 stack, a low privilege level referred to as ring 3 which has associated With it a ring 3 stack, and data registers, the computer system further including a secondary stack, memory, a programmable interrupt controller which includes an in-service register indicating the current hardware interrupt being serviced, wherein the computer system maintains a virtual copy of the in-service register in the memory, wherein the memory further includes a virtual 8086 task operating at ring 3 level and a task state segment associated with the task which includes a ring 0 stack pointer that points to the beginning of the ring 0 stack, the ring 0 code and the virtual 8086 task each having an associated task state, the method comprising:

(a) transitioning from virtual 8086 mode to protected mode to execute the ring 0 code;

(b) retrieving the ring 0 stack pointer after transitioning from virtual 8086 mode to protected mode;

(c) placing the virtual 8086 task state on the ring 0 stack after retrieving the ring 0 stack pointer;

(d) pushing a pointer to said virtual 8086 task state on the secondary stack after placing said virtual 8086 task state;

(e) enabling interrupts and beginning execution of said ring 0 code after pushing said pointer;

(f) saving the ring 0 code task state on the ring 0 stack after occurrence of an exceptional condition after enabling interrupts and beginning execution;

(g) checking the status of the in-service register virtual copy after saving said ring 0 code task state to determine if said exceptional condition is a hardware interrupt;

(h) saving certain data register values on the ring 0 stack if said exceptional condition is a hardware interrupt as determined in step (g);

(i) retrieving the most recent virtual 8086 task state pointer on the secondary stack after saving said certain data register values;

(j) copying the virtual 8086 task state pointed to by said most recent virtual 8086 task state pointer on the top of the ring 0 stack after retrieving said most recent virtual 8086 task state pointer;

(k) determining the entry address of an interrupt service routine required to service said hardware interrupt after occurrence of said exceptional condition;

(l) modifying said copied virtual 8086 task state to indicate execution at said interrupt service routine entry address after determining said entry address;

(m) modifying the ring 0 stack pointer to point to said copied and modified virtual 8086 task state on the ring 0 stack after copying said virtual 8086 task state;

(n) appending a pointer to the ring 3 stack after occurrence of said exceptional condition, wherein said ring 3 stack pointer causes execution to proceed to an end of interrupt routine that traps back to protected mode and further causes end of interrupt routine task information to be placed on the ring 0 stack;

(o) entering virtual 8086 mode and beginning execution of said interrupt service routine after appending said pointer;

(p) executing the interrupt service routine, during which time interrupts may be enabled, wherein an exceptional condition occurring during said interrupt service routine causes steps (a) through (e) to be repeated;

(q) popping said ring 3 stack pointer off of the ring 3 stack to execute said end of interrupt routine and return to protected mode after completion of said interrupt service routine;

(r) discarding said end of interrupt routine task information placed on the ring 0 stack by said entry to protected mode after returning to protected mode;

(s) modifying the ring 0 stack pointer to the pointer value most recently placed on the secondary stack after returning to protected mode;

(t) restoring said saved data register values from the ring 0 stack after returning to protected mode;

(u) returning execution to the ring 0 code using the ring 0 task state on the ring 0 stack after restoring said saved data register values, wherein an exceptional condition would cause steps (f) through (p) to be repeated;

(v) retrieving the most recent pointer from the top of the secondary stack upon completion of the ring 0 code; and

(w) returning to the virtual 8086 mode task or interrupt service routine using the virtual 8086 task state information on the ring 0 stack pointed to by said most recent pointer retrieved from the secondary stack in step (v) after completion of the ring 0 code.