Microprocessor auxiliary with combined pin for reset output and pushbutton input

• US 5,303,390 A
• Filed: 06/28/1990
• Issued: 04/12/1994
• Est. Priority Date: 06/28/1990
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Little, Wendell L.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Lo, Allen
• Application Number:
  US07/546,213
• Time in Patent Office: 1,384 Days
• Field of Search: 364/200, 364/230.4, 364/264, 364/264.7, 364/267.9, 364/273.4, 371/12, 307/296.4, 361/88, 361/93
• US Class Current: 714/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A system which includes not only a microprocessor (or microcontroller), but also an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor, and also provides a watchdog function to monitor the microprocessor'"'"'s activity. The auxiliary chip uses only two pins for the three functions of:

active-high-reset out,

active-low-reset out, and

pushbutton reset input.

Claims

1. An integrated circuit, for performing power management functions, comprising:

a voltage comparison circuit, connected to monitor the voltage of an external power supply node with reference to a reference-voltage source;

a watchdog timer circuit, connected to detect inactivity of more than a minimum duration on a predetermined input node;

reset control logic, connected to reset nodes;

interrupt generation logic, connected to an interrupt node;

and wherein said reset nodes include both an active-high reset node and an active-low reset node;

and further comprising a debounce circuit connected to said active-low reset node;

wherein when said watchdog timer circuit detects inactivity of more than a minimum duration said reset control logic generates a low pulse at said active-low reset node, and when said debounce circuit detects a low signal at said active-low reset node not generated by said reset control logic, said reset control logic generates a low pulse at said active-low reset node.

2. The integrated circuit of claim 1, wherein said debounce circuit comprises a one-shot.

3. The integrated circuit of claim 1, wherein said voltage comparison circuit comprises multiple comparators.

4. The integrated circuit of claim 1, wherein said reference-voltage source is a bandgap-voltage-reference.

5. The integrated circuit of claim 1, further comprising chip-enable control logic, connected to receive an externally generated chip-enable input signal, and to provide corresponding chip-enable outputs externally only if said comparison circuit indicates that the external power supply voltage is sufficiently near said target voltage.

6. The integrated circuit of claim 1, further comprising sleep control logic, connected to selectably place said auxiliary integrated circuit into a sleep mode by disabling multiple circuits thereof, including said watchdog timer circuit.

7. A system, comprising:

a complex programmable integrated circuit;

an auxiliary integrated circuit, which is connected to provide reset and/or interrupt signals to said complex integrated circuit, and which comprises;

a voltage comparison circuit, connected to monitor the voltage of an external power supply node with reference to a reference-voltage source;

a watchdog timer circuit, connected to detect inactivity of more than a minimum duration on a predetermined input node;

reset control logic, connected to reset nodes;

interrupt generation logic, connected to an interrupt node;

and wherein said reset nodes include both an active-high reset node and an active-low reset node;

and further comprising a debounce circuit connected to said active-low reset node;

wherein when said watchdog timer circuit detects inactivity of more than a minimum duration said reset control logic generates a low pulse at said active-low reset node, and and

at least one manually actuable electrical switch, connected to one of said reset nodes of said auxiliary integrated circuit.

8. The system of claim 7, further comprising an input channel, connected to provide data inputs to said complex integrated circuit, and an output channel, connected so that said complex integrated circuit can provide outputs therethrough to one or more storage devices, channel interfaces, processors, and/or users.

9. The system of claim 7, wherein said complex integrated circuit is a microprocessor.