Method of forming a gate overlap LDD structure

• US 5,304,504 A
• Filed: 06/02/1993
• Issued: 04/19/1994
• Est. Priority Date: 12/18/1991
• Status: Expired due to Term

• Current Assignee: Ishikawajima-Harima Heavy Industries Company Limited
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Sundaresan, Ravishankar, Wei, Che-Chia
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/071,563
• Time in Patent Office: 321 Days
• Field of Search: 437/44, 437/40, 437/27, 437/28, 437/29, 437/193, 437/233, 437/913, 257/388, 257/346
• US Class Current: 438/303
• CPC Class Codes: B01D 61/025 Reverse osmosis; Hyperfiltration
• CPC Class Codes: B01D 61/081 used at home, e.g. kitchen
• CPC Class Codes: B01D 61/12 Controlling or regulating

Abstract

A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

Claims

1. A method of forming a gate overlap LDD structure of an integrated circuit, comprising the steps of:

forming an oxide layer over a substrate;

forming a four layer stacked gate electrode over the oxide layer having an inverse-T shape wherein a first conductive layer overlies a portion of the oxide layer, a second conductive layer overlies the first conductive layer, a third conductive layer overlies a portion of the second conductive layer and a fourth conductive layer overlies the third conductive layer;

forming sidewall oxide spacers on the sides of the third and fourth conductive layers and on top of the second conductive layer; and

,

forming source/drain regions in the substrate adjacent to the gate electrode wherein the source/drain regions have lightly doped drain regions adjacent to the third and fourth conductive layers.

2. The method of claim 1, wherein the first and third conductive layers comprise polysilicon.

3. The method of claim 1, wherein the first and third conductive layers comprise amorphous silicon.

4. The method of claim 1, wherein the second and fourth conductive layers comprise a refractory metal.

5. The method of claim 4, wherein the refractory metal comprises tungsten.

6. The method of claim 4, wherein the refractory metal comprises titanium nitride.

7. The method of claim 1, wherein the lightly doped drain regions are formed before the sidewall oxide spacers are formed.

8. A method of forming a gate overlap LDD structure of an integrated circuit, comprising the steps of:

forming an oxide layer over a substrate;

forming a first polysilicon layer over the oxide layer;

forming a first conductive layer over the first polysilicon layer;

forming a second polysilicon layer over the first conductive layer;

forming a second conductive layer over the second polysilicon layer;

patterning and etching the second conductive and polysilicon layers to expose a portion of the underlying first conductive layer;

forming lightly doped drain regions in the substrate adjacent to the second conductive and polysilicon layers;

forming sidewall oxide spacers on the sides of the second conductive and polysilicon layers and on top of the first conductive layer;

etching the first conductive and polysilicon layers exposing a portion of the oxide layer; and

,

forming source/drain regions in the substrate under and adjacent to the first conductive and polysilicon layers.

9. The method of claim 8, wherein the first and second conductive layers comprises a refractory metal.

10. The method of claim 9, wherein the refractory metal comprises tungsten.

11. The method of claim 9, wherein the refractory metal comprises titanium nitride.

12. The method of claim 8, wherein the lightly doped drain regions are doped with an N^- dopant.

13. The method of claim 8, wherein the source/drain regions are doped with an N⁺ dopant.