Bipolar ESD protection for integrated circuits

• US 5,304,839 A
• Filed: 03/06/1992
• Issued: 04/19/1994
• Est. Priority Date: 12/04/1990
• Status: Expired due to Term

• Current Assignee: AT&T IPM Corp. (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Smooha, Yehuda, Morris, Bernard L., Gabara, Thaddeus J., Chen, Che-Tsung
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/847,438
• Time in Patent Office: 774 Days
• Field of Search: 357/23.13, 257/355, 257/360, 257/362, 257/363, 257/546, 257/566, 257/577, 257/356
• US Class Current: 257/546
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements

Abstract

CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V_SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Claims

1. An integrated circuit formed in a semiconductor body, and having a conductive bondpad that is coupled to at least one of input or output circuitry, wherein an electrostatic discharge (ESD) protection means is connected to said bondpad for conducting an electric charge from said bondpad to a negative (V_SS) power supply conductor on said integrated circuit when the positive voltage on said bondpad exceeds a given limit,

characterized in that said electrostatic discharge protection means comprises a pnp bipolar transistor having:

an n-type base region located in an n-type tub region that is located in a p-type substrate;

a heavily doped p-type emitter region formed directly in said n-type tub and connected to said bondpad through a conductor formed in a window in an overlying dielectric;

and a p-type collector region that is connected to said negative power supply conductor;

wherein said pnp bipolar transistor has its collector formed in a p-type tub region located adjacent to said n-type tub region in said semiconductor body;

wherein said base is connected to said bondpad by means comprising a heavily doped n-type contact region formed in said n-type tub region;

whereby a delay means is formed comprising a resistance in said n-type tub between said contact region and said emitter, and also comprising a capacitance between said n-type tub and said p-type substrate;

and whereby said bipolar transistor become highly conducting during a positive voltage ESD event, and becomes significantly less conducting when normal operating voltages are applied to said bondpad.

2. The integrated circuit of claim 1 wherein said bipolar transistor becomes highly conducting for a time period that is less than 100 nanoseconds following the beginning of a given ESD event.

3. The integrated circuit of claim 1 wherein said bipolar transistor becomes highly conducting for a time period that is at least 100 picoseconds after the beginning of a given ESD event.