Method for powering down a microprocessor embedded within a gate array

• US 5,304,860 A
• Filed: 10/12/1993
• Issued: 04/19/1994
• Est. Priority Date: 04/29/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Steininger, Franz, Ashby, Laurin R.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/135,637
• Time in Patent Office: 189 Days
• Field of Search: 307/443, 307/465, 307/465.1, 307/475, 307/296.3, 307/296.4, 395/800, 364/489-491
• US Class Current: 327/545
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.

Claims

1. A method for providing a power down mode for a microprocessor embedded within a gate array, the microprocessor having a plurality of inputs and a plurality of outputs, the gate array also including an ASIC cell block which remains active when the microprocessor is powered down, the method comprising the steps of:

providing separate and independent power supply means for the microprocessor and the ASIC cell block;

isolating the microprocessor from the ASIC cell block;

removing power to the microprocessor during the power down mode; and

maintaining the plurality of inputs and the plurality of outputs of the microprocessor at predetermined logic voltage levels during the power down mode.

2. The method according to claim 1 wherein the step of providing separate and independent power supply means includes the steps of:

providing separate and independent power supply pins for the microprocessor and the ASIC cell block; and

providing separate and independent power supply busses for the microprocessor and the ASIC cell block;