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CMOS input buffer with high speed and low power

  • US 5,304,867 A
  • Filed: 12/12/1991
  • Issued: 04/19/1994
  • Est. Priority Date: 12/12/1991
  • Status: Expired due to Term
First Claim
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1. An integrated circuit having an input buffer comprising an input inverter having a p-channel field effect transistor serially connected with an n-channel field effect transistor that are coupled to receive an input signal, and an output inverter coupled to a buffer output node,Characterized in that said buffer further comprises a current-limiting transistor biased to conductor and directly connected in series between a controlled electrode of a first one of the complementary transistors of said input inverter and a power supply conductor;

  • and still further comprises a shunt transistor having controlled electrodes connected in parallel with said current-limiting transistor and having a control electrode coupled to said buffer output node.

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