BiCMOS digital amplifier

• US 5,304,869 A
• Filed: 04/17/1992
• Issued: 04/19/1994
• Est. Priority Date: 04/17/1992
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Greason, Jeffrey K.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US07/870,568
• Time in Patent Office: 732 Days
• Field of Search: 307/494, 307/495, 307/446, 307/455, 330/300, 330/311, 330/283, 330/257
• US Class Current: 326/66
• CPC Class Codes: H03K 19/017518 using a combination of bipolar and field effect transistors [BIFET]

Abstract

A BiCMOS circuit for amplifying the difference voltage between two input voltage signals. The BiCMOS circuit of the present invention includes two bipolar junction transistor which receive the two input voltage signals and each drive a cascode-connected PMOS device. The drains of the cascode-connected PMOS devices are coupled to the input and output of a current mirror, wherein the output of the current mirror is the output of the BiCMOS circuit.

Claims

1. A BiCMOS circuit architecture for amplifying the difference voltage between first and second input signals having an input level;

first and second emitter followers coupled to an operating potential, wherein the bases of said first and second transistors are connected to the first and second input signals respectively, wherein a current gain is provided, such that the circuit operates at low voltages, wherein said first and second emitter followers generate first and second currents respectively in response to said first and second input signals respectively; and

third and fourth transistors cascode connected to said first and second transistors to receive the first and second currents, wherein said third and fourth transistors are biased by a first potential independent of the input level of the first and second input signals, and wherein the gate-to-source voltage over each of said third and fourth transistors is increased by lowering the first potential, said third and fourth transistors producing third and fourth currents respectively in response to the first and second currents;

current source means coupled to said third and fourth transistors for providing an output in response to said third and fourth currents, wherein said current source means includes fifth and sixth transistors coupled as a current mirror having an input and an output, wherein the drain and the gate of said fifth transistor and the gate of said sixth transistor are connected directly to said input of said current mirror without any intervening elements and said sources of said fifth and sixth transistors coupled to a first potential, and further wherein said current mirror is coupled to said third and fourth p-channel MOS transistors and said drain of said sixth transistor is coupled to said output, wherein the output is the fourth current less the third current.

2. The circuit architecture defined in claim 1 wherein said current source means includes a current mirror.

3. The circuit architecture defined in claim 2 wherein said third and fourth transistors comprise p-channel MOS transistors.

4. The circuit defined in claim 1 wherein said first and second emitter of followers comprise first and second bipolar transistors.

5. A BiCMOS circuit architecture for amplifying the difference voltage between first and second input signals comprising:

first and second bipolar junction transistors, each of said first and second transistors configured as an emitter follower, wherein the bases of said first and second transistors are coupled to said first and second input signals respectively, said first and second transistors generating first and second currents in response to said first and second input signals respectively;

third and fourth p-channel MOS transistors cascode connected to said first and second transistors respectively, said third and fourth transistors generating third and fourth currents respectively in response to said first and second currents respectively; and

fifth and sixth transistors coupled as a current mirror having an input and an output, wherein the drain and the gate of said fifth transistor and the gate of said sixth transistor are connected directly to said input of said current mirror without any intervening elements and said drain of said sixth transistor is coupled to said output, said sources of said fifth and sixth transistors coupled to a first potential, said current mirror being coupled to said third and fourth p-channel MOS transistors, such that said current mirror generates a current on the drain of said sixth transistor which is equal to said third current and the current at said output is the sum of said third and fourth currents.

8. The circuit architecture defined in claim 5 wherein each of said fifth and sixth transistors comprises a MESFET.

9. The circuit architecture defined in claim 5 wherein each of said fifth and sixth transistors comprises an n-channel MOS transistor.

10. The circuit architecture defined in claim 5 wherein each of said fifth and sixth transistors comprises an NPN device.

6. A BiCMOS circuit architecture for amplifying the difference voltage between first and second input signals comprising:

first and second metal semiconductor field effect transistors (MESFET), each of said first and second transistors configured as an emitter follower, wherein the bases of said first and second transistors are coupled to said first and second input signals respectively, said first and second transistors generating first and second currents in response to said first and second input signals respectively;

third and fourth p-channel MOS transistors cascode connected to said first and second transistors respectively, said third and fourth transistors generating third and fourth currents respectively in response to said first and second currents respectively; and

fifth and sixth transistors coupled as a current mirror having an input and an output, wherein the drain and the gate of said fifth transistor and the gate of said sixth transistor are connected directly to said input of said current mirror without any intervening elements and said drain of said sixth transistor is coupled to said output, said sources of said fifth and sixth transistors coupled to a first potential, said current mirror being coupled to said third and fourth p-channel MOS transistors, such that said current mirror generates a current on the drain of said sixth transistor which is equal to said third current and the current at said output is the sum of said third and fourth currents.

7. A BiCMOS circuit architecture for amplifying the difference voltage between first and second input signals comprising:

first and second junction field effect transistors (JFET), each of said first and second transistors configured as an emitter follower, wherein the bases of said first and second transistors are coupled to said first and second input signals respectively, said first and second transistors generating first and second currents in response to said first and second input signals respectively;

third and fourth p-channel MOS transistors cascode connected to said first and second transistors respectively, said third and fourth transistors generating third and fourth currents respectively in response to said first and second currents respectively; and

fifth and sixth transistors coupled as a current mirror having an input and an output, wherein the drain and the gate of said fifth transistor and the gate of said sixth transistor are connected directly to said input of said current mirror without any intervening elements and said drain of said sixth transistor is coupled to said output, said sources of said fifth and sixth transistors coupled to a first potential, said current mirror being coupled to said third and fourth p-channel MOS transistors, such that said current mirror generates a current on the drain of said sixth transistor which is equal to said third current and the current at said output is the sum of said third and fourth currents.

11. A BiCMOS circuit architecture for amplifying the difference voltage between first and second input signals comprising:

first and second bipolar transistors, each of said first and second bipolar transistors configured as an emitter follower, wherein the bases of said first and second transistors are coupled to said first and second input signals respectively and the collectors are coupled to a first potential, said first and second transistors generating first and second currents in response to said first and second input signals respectively and said first potential;

third and fourth p-channel MOS transistors cascode connected to said first and second transistors respectively, said third and fourth transistors generating third and fourth currents respectively in response to said first and second currents respectively; and

fifth and sixth n-channel MOS transistors, said fifth and sixth transistors coupled as a current mirror having an input and an output, wherein the drain and the gate of said fifth transistor and the gate of said sixth transistor are connected directly to said input of said current mirror without any intervening elements and said drain of said sixth transistor is coupled to said output, said sources of said fifth and sixth transistors coupled to a second potential, said current mirror being coupled to said third and fourth transistors, such that said current mirror generates a current on the drain of said sixth transistor which is equal to said third current and the current at said output is the sum of said third and fourth currents.

12. The circuit defined in claim 11 wherein said output is CMOS compatible.