RF amplifier with linear gain control

• US 5,304,948 A
• Filed: 12/11/1992
• Issued: 04/19/1994
• Est. Priority Date: 12/11/1992
• Status: Expired due to Term

• Current Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Mucke, Lars H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/989,116
• Time in Patent Office: 494 Days
• Field of Search: 330/145, 330/284, 333/81 R, 307/559, 307/561, 307/565
• US Class Current: 330/284
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03G 7/001 without controlling loop H03G7/007, H03G7/02, H03G7/06 take precedence

Abstract

A circuit amplifies an input RF band of signals and exhibits a signal gain in decibels that is a linear function of the logarithm of a control signal input. The circuit comprises a first amplifier stage having an output node that exhibits a first RF complex admittance within the RF band of signals. A second amplifier stage has an input node coupled to the output node of the first amplifier stage and exhibits a second RF complex admittance within the RF band of signals. A PIN diode, used as a gain control element, is shunt connected between the control signal input and the output node. An RF reactance circuit is also shunt connected between the output node and a common potential. The RF reactance circuit has a third admittance that is chosen to negate the imaginary portions of the first and second complex admittances, whereby the total admittance is substantially real and enables the PIN diode to see a minimal resistive load.

Claims

1. A circuit for amplifying an input radio frequency (RF) band of signals, wherein signal gain in decibels (dB) is a linear function of the logarithm of a control signal, said circuit comprising:

a first transistor amplifier stage having an output node exhibiting a first RF complex admittance within said frequency band of signals;

a second transistor amplifier stage having a control electrode, a second electrode coupled to a power supply and a third electrode coupled through a resistance to a common potential, said control electrode coupled to said output node and exhibiting a second RF complex admittance within said frequency band of signals;

PIN diode means connected between a control signal input and said output node and responsive to a control signal to reflect a given RF admittance, said PIN diode means further connected via an RF path to said common potential; and

RF reactance means shunt connected with respect to said PIN diode means, between said common potential and said output node, said RF reactance means having a third RF complex admittance that is chosen to negate imaginary portions of said first and second complex admittances, whereby any admittance seen by said PIN diode means is substantially real within said frequency band of signals.

2. The circuit as described in claim 1 wherein variations in said control signal input act to vary the RF resistance of said PIN diode means to thereby shunt portions of said radio frequency band of signals to said common potential, said variation resulting in a linear change of gain.

3. The circuit as described in claim 2 wherein said RF reactance means comprises a parallel connected inductor/capacitor pair.

4. The circuit as described in claim 3 wherein said given RF admittance of said PIN diode means is much larger than either of said first or second RF complex admittances.

5. The circuit as recited in claim 2 further comprising a resistance connecting said PIN diode means to said common potential and providing a constant current path for a first portion of said control signal, said control signal input being a dc current and having a second portion that is variable, such that when said variable portion is small and changes therein occur, said PIN diode means experiences a change in admittance through combined effects of said first portion and second portion of said control signal that offsets nonlinearities in gain control that result from any admittances seen by said PIN diode means.

6. The circuit as described in claim 1 wherein said first and second amplifier stages comprise MOSFET transistors, with a terminal of a MOSFET transistor in said first amplifier stage being in RF communication with a gate of a MOSFET transistor in said second amplifier stage, both said MOSFETS exhibiting real part admittances that are small in relationship to a real part admittance exhibited by said PIN diode means.

7. The circuit as recited in claim 1 wherein said first and second amplifier stages comprise bipolar transistors, a bipolar transistor in said first amplifier stage having its collector in RF communication with a base of a bipolar transistor in said second amplifier stage, said bipolar transistors exhibiting a small base to collector feedback capacitance.

8. The circuit as recited in claim 7 wherein said bipolar transistor in said second amplifier stage has its emitter connected via said resistance to said common potential, the value of said resistance, in combination with a beta value for said second transistor, acting to create a low input admittance at the base of said bipolar transistor in said second amplifier circuit.