Divider synchronization circuit for phase-locked loop frequency synthesizer

• US 5,304,951 A
• Filed: 01/31/1992
• Issued: 04/19/1994
• Est. Priority Date: 01/31/1992
• Status: Expired due to Term

• Current Assignee: Microelectronics Technology Inc (MTI Laboratory Inc)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Cosand, Albert E.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/829,183
• Time in Patent Office: 809 Days
• Field of Search: 331/1 A, 331/14, 331/16, 331/25
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 7/189 comprising a D/A converter for generating a coarse tuning voltage
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

A divider synchronization circuit (11) that provides faster settling to a new frequency in a phase-locked loop frequency synthesizer (10) that uses a programmable divider (16) and a phase detector (17). The circuit (11) is adapted to stop the divider (16) while its program is being changed, and then restart the divider (16) on command. The startup time of the divider (16) is automatically adjusted such that the divider output is in phase with a reference input to a phase detector (17). The outputs of the phase detector (17) are also blanked during the time period that the divider (16) is stopped. The circuit (11) reduces the time required for the phase locked-loop frequency synthesizer (10) to settle to its new frequency and phase when the frequency is changed. The timing of the divider startup eliminates the large phase transient that may occur when the divider startup timing is random, thus shortening the time that must be allowed for the synthesizer output to settle to its final phase. This circuit (11) is of particular value in a fast settling synthesizer design in which a VCO is pretuned to a close approximation to the new output frequency and then the loop is closed to drive the frequency to its exact value. The circuit (11) is well adapted for use in spread spectrum and frequency-agile radar systems, or spread spectrum communications systems.

Claims

1. A divider synchronization circuit for use with a phase-locked loop frequency synthesizer (10) comprising a programmable divider (16) and a phase detector (17), said divider synchronization circuit comprising:

detection means (21, 22, 23, 24,

     25) for receiving a reference frequency signal input, and a synchronizing signal that comprises a command signal that causes a frequency change to occur, for detecting a time at which the reference frequency signal makes a transition that is used as a phase reference against which the output of the programmable divider (16) is compared;

a first gate (28) having first and second inputs and an output, and having its first input coupled to a first output of the detection means (21, 22, 23, 24,

     25) and its second input adapted to receive a latch enable signal, and having its output adapted to provide a latch enable signal for use by the programmable divider that is adapted to latch its programming inputs while the startup time of the divider (16) is adjusted so that its output is in phase with the reference frequency signal input to the phase detector (17); and

a second gate (29) having first and second inputs and an output, and having its first input coupled to a second output of the detection means (21, 22, 23, 24,

     25) and its second input adapted to receive a divide enable signal, and having its output adapted to provide divide enable and phase detector blanking signals for use by the programmable divider (16) and phase detector (17), respectively, that is adapted to reset the divider (16) and blank the phase detector (17);

and whereby the divide enable signal is adapted to cause the interruption of the divider (16) while its program is being changed and then restart the divider (16), and wherein the outputs of the phase detector (17) are blanked using the phase detector (17) blanking signal during the time that the divider (16) is interrupted, and whereby the startup time of the divider (16) is adjusted so that the output of the divider (16) is substantially in phase with the reference frequency signal input to the phase detector (17).

2. The divider synchronization circuit of claim 1 wherein the detection means (21, 22, 23, 24, 25) comprises:

a first rising edge detector (21) having an input and an output, that is adapted to receive a reference frequency signal;

a first latch (22) having a plurality of inputs and an output that comprises the second output of the detection means, and having a first input coupled to the output of the first rising edge detector (21) and having a second input coupled to receive the synchronizing signal that is adapted to cause a frequency change to occur;

a second rising edge detector (24) having an input and an output, that is adapted to receive the synchronizing signal; and

a one-shot circuit (31) coupled to the outputs of the first and second rising edge detectors (21,

     22) that is adapted to receive a divide enable signal and provide an enabling output signal from the first output of the detection means.

3. The divider synchronization circuit of claim 1 wherein the detection means (21, 22, 23, 24, 25) comprises:

a resettable edge-triggered flip flop (40b) having a plurality of inputs and an output, and having a high signal coupled to a first input, a synchronizing input coupled to a second input, a reference frequency signal coupled to a clock input, and an output taken from its Q output.

4. The divider synchronization circuit of claim 2 wherein the one-shot circuit (31) comprises:

a second latch (25) having S and R inputs and a Q output, and having its S input coupled to the output of the second rising edge detector (24);

an inverter (26) having an input coupled to the Q output of the second latch (25);

a third latch (23) having S and R inputs and a Q output, and having its S input coupled to the output of the first rising edge detector (21) and having its R input coupled to the output of the inverter (26); and

a delay circuit (27) having an input coupled to the Q output of the third latch (23) and having its output coupled to the R input of the second latch (25).

5. A divider synchronization circuit for use with a phase-locked loop frequency synthesizer (10) comprising a programmable divider (16) and a phase detector (17), said divider synchronization circuit comprising:

detection means (21, 22, 23, 24,

     25) for receiving a reference frequency signal input, and a synchronizing signal that comprises a command signal that causes a frequency change to occur, for detecting a time at which the reference frequency signal makes a transition that is used as a phase reference against which the output of the programmable divider (16) is compared, and wherein the detection means (21, 22, 23, 24,

     25) comprises;

a first rising edge detector (21) having an input and an output, that is adapted to receive a reference frequency signal;

a first latch (22) having a plurality of inputs and an output that comprises the second output of the detection means, and having a first input coupled to the output of the first rising edge detector (21) and having a second input coupled to receive the synchronizing signal that is adapted to cause a frequency change to occur;

a second rising edge detector (24) having an input and an output, that is adapted to receive the synchronizing signal; and

a one-shot circuit (31) coupled to the outputs of the first and second rising edge detectors (21,

     22) for providing an enabling output signal from the first output of the detection means;

a first gate (28) having first and second inputs and an output, and having its first input coupled to a first output of the detection means (21, 22, 23, 24,

     25) and its second input adapted to receive a latch enable signal, and having its output adapted to provide a latch enable signal for use by the programmable divider that is adapted to latch its programming inputs while the startup time of the divider (16) is adjusted so that its output is in phase with the reference frequency signal input to the phase detector (17); and

a second gate (29) having first and second inputs and an output, and having its first input coupled to a second output of the detection means (21, 22, 23, 24,

     25) and its second input adapted to receive a divide enable signal, and having its output adapted to provide divide enable and phase detector blanking signals for use by the programmable divider (16) and phase detector (17), respectively, that is adapted to reset the divider (16) and blank the phase detector (17);

and whereby the divide enable signal is adapted to cause the interruption of the divider (16) while its program is being changed and then restart the divider (16), and wherein the outputs of the phase detector (17) are blanked using the phase detector (17) blanking signal during the time that the divider (16) is interrupted, and whereby the startup time of the divider (16) is adjusted so that the output of the divider (16) is substantially in phase with the reference frequency signal input to the phase detector (17).

6. The divider synchronization circuit of claim 5 wherein the detection means (21, 22, 23, 24, 25) comprises:

a resettable edge-triggered flip flop (40b) having a plurality of inputs and an output, and having a high signal coupled to a first input, a synchronizing input coupled to a second input, a reference frequency signal coupled to a clock input, and an output taken from its Q output.

7. The divider synchronization circuit of claim 6 wherein the one-shot circuit (31) comprises:

a second latch (25) having S and R inputs and a Q output, and having its S input coupled to the output of the second rising edge detector (24);

an inverter (26) having an input coupled to the Q output of the second latch (25);

a third latch (23) having S and R inputs and a Q output, and having its S input coupled to the output of the first rising edge detector (21) and having its R input coupled to the output of the inverter (26); and

a delay circuit (27) having an input coupled to the Q output of the third latch (23) and having its output coupled to the R input of the second latch (25).