Drive circuit for zero-voltage switching power converter with controlled power switch turn-on

• US 5,305,191 A
• Filed: 04/20/1992
• Issued: 04/19/1994
• Est. Priority Date: 04/20/1992
• Status: Expired due to Fees

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Loftus, Thomas P. Jr.
• Primary Examiner(s): Voeltz, Emanuel T.
• Application Number:
  US07/871,370
• Time in Patent Office: 729 Days
• Field of Search: 363/16, 363/17, 363/98, 363/132, 307/239, 307/571, 307/575, 307/576, 307/583, 307/584, 307/585, 307/590, 307/605
• US Class Current: 363/17
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 3/3376 with automatic control of output voltage or current
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A drive arrangement and operative scheme for the power switching transistors of a half-bridge power drives the two power switching transistors with unequal duty cycles having conducting durations such that the sum of the conduction intervals substantially equals the combined switching period of the two power switching transistors. The conducting intervals are separated by very short dead time intervals controlled by the differing turn-on and turn-off times of the two power switching transistors. The short interval between alternate conductions of the two power switching transistors is sufficient to allow zero voltage turn on of the power switching transistors but short enough to minimize power loss and conducted noise.

Claims

1. A DC-DC power converter comprising:

A power switching stage,

an input for coupling a DC voltage to the power switching stage

a power transformer having a primary and secondary winding;

An FET power switch for coupling the input to the primary winding;

a drive circuit for the FET power switch including;

a drain, a source and a gate electrode;

a drain-source parasitic capacitance;

a circuit arrangement utilizing feedback of the current output of the discharging drain source parasitic capacitance to generate a voltage drop across a resistor connected to the gate electrode to clamp the gate electrode below a turn-on voltage of the FET power switch.

2. A DC-DC power converter as claimed in claim 1, comprising:

a discrete capacitance connected in shunt with the parasitic capacitance.

3. A DC-DC power converter as claimed in claim 2, comprising:

the parasitic capacitance including a miller capacitance of the FET power switch.

4. A power converter, comprising:

an input and an output,

an FET power switch having drain, source and gate electrodes and having its drain-source electrodes connected for controlling power flow between the input and the output,

the FET power switch including drain-source parasitic capacitance, drain-gate parasitic capacitance, and gate-source parasitic capacitance,

a discrete capacitor and a miller capacitance shunting the drain-gate electrodes of the FET power switch,

a source of drive signals,

control circuitry for timing initiation of drive signals generated by the source of drive signals so that drive signals coincide with a minimum voltage across the drain-source electrodes of the FET power switch,

a resistive impedance coupling the source of drive signals to the gate electrode of the FET power switch and having a resistive value so that the current drain of the drain-source parasitic capacitance through the paralleled drain-gate parasitic capacitance, the miller capacitance and the discrete generates a voltage drop across the resistive impedance to maintain voltage of the gate electrode below a turn-on threshold of the FET power switch until the drain-source parasitic capacitance current discharge terminates at the minimum voltage.

5. A power converter;

comprising;

a power switching stage including;

a first and second FET power switch connected in a bridge power switching circuit;

each FET power switch having drain, source and gate electrodes and having its drain-source electrodes connected in a power flow path of the bridge power switching circuit;

the first and second FET power switches each including drain-source parasitic capacitance, drain-gate parasitic capacitance and gate-source parasitic capacitance;

a discrete capacitor and a miller capacitance shunting the drain-gate electrodes of each of the first and second FET power switches,

drive circuitry for supplying drive signals for driving the first and second FET power switches into conduction at different time intervals;

control circuitry for timing initiation of drive signals generated by the source of drive signals so that drive signals coincide with a minimum voltage across the drain-source electrodes of the first and second FET power switches,

a resistive impedance coupling the source of drive signals to the gate electrode of each of the first and second FET power switches and having a resistive value so that the current drain of the drain-source parasitic capacitance through the paralleled drain-gate parasitic capacitance, the miller capacitance and the discrete capacitor generates a voltage drop across the resistive impedance to maintain voltage of the gate electrode below a turn-on threshold of the FET power switch until the drain-source parasitic capacitance current discharge terminates at the minimum voltage.