Switch-level timing simulation based on two-connected components

• US 5,305,229 A
• Filed: 09/06/1991
• Issued: 04/19/1994
• Est. Priority Date: 09/06/1991
• Status: Expired due to Term

• Current Assignee: TTI Inventions B LLC (Intellectual Ventures LLC)
• Original Assignee: Bell Communications Research, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Dhar, Sanjay
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US07/756,078
• Time in Patent Office: 956 Days
• Field of Search: 364/489, 364/578, 364/491, 364/488
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.

Claims

1. A method of simulating a circuit of transistors and reference terminals and determining driving-point resistances in linear time and space, said method comprising the steps, executed by a data processor having memory means, of

generating a model of the transistor circuit as an RC-network representation of the transistor circuit, said representation being other than an RC-tree network and comprising a plurality of switches each corresponding to a different one of the transistors and each of the switches containing a gate and two nodes connected by a corresponding channel having a resistance value such that each channel is considered conducting or nonconducting according to the state of the corresponding gate;

storing in said circuit memory means said representation of the transistor circuit including said resistance value for each of said channels;

defining a state configuration for a given state of the RC-network representation, the defined state configuration containing channels which would be considered conducting in that given state and nodes connected to the conducting ones of the channels;

determining, from the resistance values for the channels in the defined state configuration, the driving point resistances between each of the nodes in the defined state configuration and the reference terminals; and

each of said nodes having a corresponding capacitance value, determining the delay for the transition from the given state tot he next state from the driving point resistances in the defined state configuration and from the capacitance values of the nodes contained in the defined state configuration;

whereby the time required for said method is essentially proportional to the number of nodes and the circuit memory means required for said method is also essentially proportional to the number of nodes.

2. The method of claim 1 ,wherein the step of determining corresponding driving-point resistances for each of the nodes includes the substeps of

determining, for each of the nodes, a first driving-point resistance between the corresponding node and a first one of the reference terminals for the given configuration;

and

determining, for each of the nodes, a second driving-point resistance between the corresponding node and a second one of the reference terminals for the given configuration.

3. The method of claim 2 wherein the state of a set of transistors is unknown and

wherein the substeps of determining the first and second driving-point resistances further include the substeps of

determining the first driving-point resistance with the channels of all the transistors in the set being in the given configuration, and

determining the second driving-point resistance with none of the channels in the set being in the given configuration.

4. A method of simulating a circuit of transistors and reference terminals and determining driving-point resistances in linear time and space, said method comprising the steps, executed by a data processor having memory means, of

generating a model of the transistor circuit as an RC-network representation of the transistor circuit, said representation being other than an RC-tree network and comprising a plurality of switches each corresponding to a different one of the transistors and each of the switches containing a gate and two nodes connected by a corresponding channel having a resistance value such that each channel is considered conducting or nonconducting according to the state of the corresponding gate;

storing in said circuit memory means said representation of the transistor circuit including said resistance value for each of said channels;

defining a state configuration for a given state of the RC-network representation by representing the transistor circuit as a graph with edges corresponding to the channels contained in the defined state configuration, the defined state configuration containing channels that would be considered conducting in that given state and nodes connecting ones of the channels;

identifying parallel paths between nodes in the graph as cycles by separating the graph into channel-connected components, separating each channel-connected component into bi-connected components, and performing series and parallel reductions on the bi-connected components to obtain a reduced graph;

determining a level of nesting for each of the identified cycles by noting the nesting levels of the cycles according to the graph reductions; and

determining from the resistance values for the channels in the defined state configuration the driving point resistances between each of the nodes in the defined state configuration and the reference terminals, including determining the driving-point resistances of the nodes in the cycles having lower levels before determining the driving point resistance of nodes in cycles having higher levels,

whereby the time required for said method is essentially proportional to the number of nodes and the circuit memory means required for said method is essentially proportional the number of nodes.

5. A method in accordance with claim 4 wherein each of the nodes has a corresponding capacitance value and further comprising determining the delay for the transistor from the given state to the next state from the driving point resistances in the defined state configuration and from the capacitance values of the nodes contained in the defined state configuration.

6. A method in accordance with claim 5 wherein the determination of the driving point resistances and of the delays involves only two traversals in opposite directions at the nodes of the RC-network representation.