Semiconductor memory with column equilibrate on change of data during a write cycle

• US 5,305,268 A
• Filed: 12/13/1990
• Issued: 04/19/1994
• Est. Priority Date: 12/13/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): KESSELL, MICHAEL
• Application Number:
  US07/627,049
• Time in Patent Office: 1,223 Days
• Field of Search: 365/203, 365/191
• US Class Current: 365/203
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V_cc, and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines.

Claims

1. A memory in an integrated circuit, comprising:

an array of memory cells arranged in rows and columns;

a plurality of pairs of bit lines, each pair associated with one of said columns, for communicating a differential signal;

a plurality of precharge transistors, each precharge transistor associated with one of said bit lines, each of said precharge transistors having a conduction path connected between its associated bit line and a precharge voltage, and having a control terminal;

a first input terminal for receiving input data;

a write circuit coupled between said first input terminal and said array, for communicating input data to the bit lines of a selected column during a write operation;

a write enable terminal for receiving a write enable signal enabling a write operation;

a data transition detection circuit, having a first input coupled to said first input terminal, for detecting a transition of the input data at the first input terminal; and

means for controlling the control terminals of said precharge transistors responsive to said data transition detection circuit in such a manner that the precharge transistors of said selected column are conductive responsive to a transition of the input data occurring during receipt of the write enable signal at said write enable terminal for a period of time prior to said write circuit communicating, to the bit lines of the selected column, input data corresponding to the input data received at said first input terminal after said transition.

2. The memory of claim 1, further comprising:

a plurality of equilibration transistors, each associated with a pair of bit lines, having a conduction path connected between its associated bit lines, and having a control terminal;

wherein said controlling means is also for controlling the control terminal of said equilibration transistors responsive to said detecting means, in such a manner that each of said equilibration transistors is conductive responsive to a transition of the input data.

3. The memory of claim 1, further comprising a second input terminal for receiving input data.

4. The memory of claim 3, wherein said

data transition detection circuit has a second input coupled to said second input terminal, for detecting transitions of input data at said second input terminal.

5. The memory of claim 1, wherein said controlling means comprises:

a column decoder, having a plurality of outputs for selecting a column in said array, responsive to a column address presented thereto, and having a control input, wherein each of the plurality of outputs of said column decoder is coupled to the control terminal of one of the precharge transistors; and

precharge control circuitry, having an input for receiving a signal from said detecting means, and having an output coupled to said control input of said column decoder so that, responsive to said detecting means detecting a transition of the input data, said column decoder causes the precharge transistors of said selected column to be conductive.

6. The memory of claim 5, wherein the outputs of said column decoder causes the precharge transistors of columns which are not selected by said column decoder to be conductive.

7. The memory of claim 5, further comprising:

address terminals, for receiving an address signal; and

an address transition detection circuit for detecting a transition at said address terminals, having inputs coupled to said address terminals and its output coupled to said precharge control circuitry;

wherein said precharge control circuitry presents a signal to the control input of said column decoder to cause said precharge transistors to be conductive responsive also to said address transition detection circuit detecting a transition.

8. A memory in an integrated circuit, comprising:

an array of memory cells arranged in rows and columns;

a plurality of pairs of bit lines, each pair associated with one of said columns, for communicating a differential signal;

a plurality of precharge transistors, each precharge transistor associated with one of said bit lines, each of said precharge transistors having a conduction path connected between its associated bit line and a precharge voltage, and having a control terminal;

means for receiving input data;

a write circuit coupled between said receiving means and said array, for communicating input data to the bit lines of a selected column during a write operation;

a write enable terminal for receiving a write enable signal indicating that a write operation is to be performed;

means for detecting a transition of the input data received by said receiving means; and

means for controlling the control terminals of said precharge transistors responsive to said detecting means, in such a manner that the precharge transistors of said selected column are conductive responsive to a transition of the input data occurring in combination with said write enable signal, comprising;

a column decoder, having a plurality of outputs for selecting a column in said array, responsive to a column address presented thereto, and having a control input, wherein each of the plurality of outputs of the column decoder is coupled to the control terminal of one of said precharge transistors; and

precharge control circuitry, having an input for receiving a signal from said detecting means, and having an output coupled to the control input of said column decoder so that, responsive to said detecting means detecting a transition of the input data, said column decoder causes the precharge transistors of the selected column to be conductive;

address terminals, for receiving an address signal; and

an address transition detection circuit for detecting a transition at said address terminals, having inputs coupled to said address terminals and its output coupled to said precharge control circuitry;

wherein said precharge control circuitry presents a signal to the control input of said column decoder to cause said precharge transistors to be conductive responsive also to said address transition detection circuit detecting a transition;

and wherein said address transition detection circuit has an output coupled to said column decoder, so that, responsive to a transition at said address terminals, all of said precharge transistors are conductive.

9. The memory of claim 8, wherein said write circuit is connected to input/output lines for communication of data to said array;

and further comprising;

input/output precharge transistors, each transistor having a conduction path connected between an associated input/output line and a precharge voltage, and having a control terminal; and

timing control circuitry, having an output coupled to sad control terminal of said input/output precharge transistors, and having an input coupled to said address transition detection circuit, so that said input/output precharge transistors are conductive responsive to a transition at said address terminals.

10. A method for operating a memory in an integrated circuit, said memory comprising a plurality of memory cells arranged in rows and columns, each of said columns associated with a pair of bit lines for communication of a differential signal thereupon, said method comprising the steps of:

selecting a column of said memory responsive to a column address;

receiving a first logic state of input data at a data input terminal;

receiving a write enable signal enabling a write operation;

during receipt of the write enable signal, receiving a second logic state of input data at said data input terminal;

responsive to receiving said second logic state of input data in combination with said write enable signal, coupling the bit lines associated with said selected column to a precharge voltage; and

then placing, onto the bit lines of the selected column, a data state corresponding to said second logic state of input data received at said data input terminal.

11. The method of claim 10, wherein said write enable signal is a pulse.

12. The method of claim 11, wherein said coupling step is performed responsive to receiving said second logic state of input data prior to the end of said write enable signal pulse.

13. The method of claim 10, wherein said memory further includes a write circuit coupled between said input data terminal and an input/output bus;

and further comprising;

responsive to receiving a new address signal, coupling lines in said input/output bus to a precharge voltage.

14. The method of claim 13, further comprising:

coupling the bit lines of said selected column to said input/output bus.

15. The method of claim 14, further comprising:

coupling the bit lines of unselected ones of said columns to said precharge voltage.

16. The method of claim 11, further comprising:

also responsive to receiving said second logic state of input data in combination with said write enable signal, coupling the bit lines associated with said selected column to one another.

17. The method of claim 10, wherein said write enable signal is a pulse;

wherein said coupling step is performed responsive to receiving said second logic state of input data prior to the end of said write enable signal pulse.

18. The method of claim 17, wherein said placing step is performed responsive to the end of said write enable signal.