Semiconductor memory device

• US 5,305,284 A
• Filed: 11/19/1992
• Issued: 04/19/1994
• Est. Priority Date: 11/21/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwase, Taira
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US07/979,054
• Time in Patent Office: 516 Days
• Field of Search: 365/238.5, 365/189.05, 365/239, 365/233.5
• US Class Current: 365/238.5
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A semiconductor memory having a page mode includes a first circuit for reading out page data from a memory cell array, in accordance with cell address signals A3-A19, and a second circuit for latching, at the beginning of a page mode cycle, page data to be read out in the cycle, sequentially outputting the latched data in page address signals A0-A2, and inputting to the first circuit an address from which to read out page data to be output in a following page mode cycle. By provision of the first and second circuits, the period of time from a change in address to output of read-out data can be shortened considerably, permitting high-speed reading in the page mode.

Claims

1. A semiconductor memory device comprising:

a first circuit for reading out page data from a cell of a memory cell array, in accordance with an address indicated by cell address signals; and

a second circuit for latching, at the beginning of a page mode cycle, first page data to be read out in the cycle, sequentially outputting the latched data in accordance with page address signals, and inputting to the first circuit an address from which to read out second page data to be output in a following page mode cycle.

3. The semiconductor memory device according to claim 1, wherein said latch signal is supplied from an address change detection circuit for detecting changes in said cell address signals.

5. The semiconductor memory device according to claim 1, wherein said latch signal is input from an external terminal.

2. A semiconductor memory device comprising:

a memory cell array;

a cell decoder connected to inputs of the memory cell array, said cell decoder for selecting a cell of the memory cell array from which page data are to be read out, in accordance with an address indicated by cell address signals;

p1 a sense amplifier group connected to outputs of the memory cell array, said sense amplifier group comprising a plurality of sense amplifiers for sensing the page data read out from the memory cell array;

a latch circuit group connected to outputs of the sense amplifier group, said latch circuit group comprising a plurality of latch circuits for latching, in response to input of a latch signal, the page data output from the sense amplifier group;

a selection group connected to outputs of said latch circuit group, said selection group comprising a plurality of selection circuits for selecting the data latched by the latch circuit group;

a page mode decoder connected to inputs of said selection group, said page mode decoder for sequentially selecting the plurality of selection circuits in accordance with page address signals;

an output buffer circuit connected to an output of said selection group, said output buffer circuit for supplying an output of a selected one of the plurality of selection circuits to an output terminal; and

a circuit for supplying said latch signal at the beginning of a page mode cycle, changing said address during the page mode cycle, and inputting to the cell decoder an address from which to read out data to be output in a following page mode cycle, wherein an output of said circuit for supplying said latch signal is an input to said latch circuit group.

4. The semiconductor memory device according to claim 2, wherein said latch signal is supplied from an address change detection circuit for detecting changes in said cell address signals.

6. The semiconductor memory device according to claim 2, wherein said latch signal is input from an external terminal.