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Semiconductor memory device

  • US 5,305,284 A
  • Filed: 11/19/1992
  • Issued: 04/19/1994
  • Est. Priority Date: 11/21/1991
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a first circuit for reading out page data from a cell of a memory cell array, in accordance with an address indicated by cell address signals; and

    a second circuit for latching, at the beginning of a page mode cycle, first page data to be read out in the cycle, sequentially outputting the latched data in accordance with page address signals, and inputting to the first circuit an address from which to read out second page data to be output in a following page mode cycle.

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