Technique for digitally detecting bit-error densities that occur in a serial bit stream

• US 5,305,323 A
• Filed: 06/25/1992
• Issued: 04/19/1994
• Est. Priority Date: 06/25/1992
• Status: Expired due to Term

• Current Assignee: Siemens Stromberg-Carlson
• Original Assignee: Siemens Stromberg-Carlson
• Inventors: Lada, Timothy P.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/904,345
• Time in Patent Office: 663 Days
• Field of Search: 371/5.1, 371/5.5, 371/5.3, 371/5.4, 371/16.5, 371/29.1, 371/47.1
• US Class Current: 714/704
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 1/24 Testing correct operation

Abstract

Apparatus, and an accompanying method, for accurately detecting bit-error densities in a serial bit stream and particularly relatively low bit-error densities. Specifically, detected bit-errors are synchronized to a bit clock using a error retiming circuit (130). Subsequently, the bit-errors are counted using a first counter (165) during a pre-defined measurement interval, equivalent to a specified number of bit clock cycles. A second counter (205) establishes the measurement interval by counting the specified number of bit clock pulses. Whenever the first counter attains a count larger than a pre-defined count, during the measurement interval, an output (alarm) signal is generated to indicate that a pre-defined threshold error density has been exceeded. Both the first and second counters are then reset at the conclusion of the measurement interval, and so on for successive measurement intervals. To assure that the measured bit-error density declines to a sufficiently low value before the output signal terminates, the measurement interval is extended once the output signal occurs. Hence, output signal is produced when the pre-defined threshold is exceeded but is reset only when the actual measured bit-error density decreases, typically by an order of magnitude, below the threshold error density.

Claims

1. Apparatus (125) for detecting a bit-error density in a serial bit stream and for producing an output signal when the bit-error density exceeds a pre-defined value, said apparatus comprising:

retiming means (130), operating in response to a bit clock signal and detected bit-errors, for synchronizing each detected bit-error to the bit clock and producing an error pulse;

first counting means (165), connected to said retiming means, for counting each error pulse occurring during a first interval;

second counting means (205) for counting a number of bit clock cycles and for establishing said first interval equivalent to said number of bit clock cycles;

means (190), connected to said first counting means, for producing an output signal whenever said first counting means attains a specified bit error count during said first interval; and

resetting means (250,

     280), connected to said first and second counting means, for resetting said first and second counting means at an end of said first interval.

2. The apparatus of claim 1 further comprising:

second interval establishing means (320) for establishing a second interval differing in duration from said first interval; and

output signal resetting means (195) for resetting said output signal producing means whenever said first counting means does not attain said specified bit error count during said second interval.

3. The apparatus of claim 2 wherein said second interval is longer than said first interval.

4. The apparatus of claim 1 wherein said second counting means comprises a plurality of divide by ten counters (220) connected in a series.

5. The apparatus of claim 1 wherein said first counting means comprises a shift register (165) having a plurality of stages (180), whereby said plurality of stages establishes said specified bit error count.

6. The apparatus of claim 1 wherein said first counting means determines a mantissa of a bit-error density and said second counting means determines an exponent of said bit-error density.

7. The apparatus of claim 2 further comprising means (250) for selecting a duration for said second interval and means (320) for selecting said first interval.

8. The apparatus of claim 7 wherein each of said selecting means further comprise data selectors (325, 260).

9. The apparatus of claim 1 further including bit-error detection means (110), responsive to said serial bit stream and connected to said retiming means, for detecting bit-errors in the serial bit stream.

10. A method for detecting a bit-error density in a serial bit stream and for producing an output signal when the bit-error density exceeds a pre-defined value, said method comprising the steps of:

synchronizing each detected bit-error with a bit clock;

converting each detected bit-error into an error pulse;

counting said error pulses occurring during a first interval using a first counter;

counting bit clock cycles using a second counter;

establishing said first interval equivalent to a specified number of bit clock cycles counted by said second counter;

producing an output signal whenever said first counter attains a specified bit error count during said first interval; and

resetting said first and second counters at an end of said first interval.

11. The method of claim 10 further comprising the steps of:

establishing a second interval different from said first interval; and

resetting said output signal whenever said first counter does not attain said specified bit error count during said second interval.

12. The method of claim 11 wherein said second interval is longer than said first interval.

13. The method of claim 11 further comprising the step of selecting a duration for said second interval and said first interval.

14. The method of claim 10 further comprising the step of detecting bit-errors in said serial bit stream.