Data logging apparatus with memory and pattern testing device

• US 5,305,331 A
• Filed: 04/12/1991
• Issued: 04/19/1994
• Est. Priority Date: 04/23/1990
• Status: Expired due to Fees

• Current Assignee: Ando Electric Co., Ltd. (Yokogawa Electric Corporation)
• Original Assignee: Ando Electric Co., Ltd. (Yokogawa Electric Corporation)
• Inventors: Ooishi, Hirohisa, Shimizu, Akira, Sato, Toshiya, Hiroi, Hajime
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Wright, Norman M.
• Application Number:
  US07/684,411
• Time in Patent Office: 1,103 Days
• Field of Search: 371/29.1, 371/25.1, 371/27, 371/16.5, 371/20.4, 371/21.2, 371/21.6, 371/24, 371/71
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A data logging apparatus for a device function tester comprises a first shift circuit (1) supplied with an output signal of the tester and a strobe signal for shifting the output of the tester by n rates under the timing of a basic clock (T₀), a second shift circuit (2) for shifting the timing of the basic clock (T₀) by n rates, a write pulse generating circuit (3) supplied with the output signal of the shift circuit (2), a third shift circuit (4) supplied with a memory address signal for shifting it by n rates under the timing of the basic clock (T₀), a fourth shift circuit (5) for shifting a pattern address signal by n rates under the timing of the basic clock (T₀), a first memory (6) supplied with the output signal of the first shift circuit (1) and the output signal of the third shift circuit (1) for storing the result of the test shifted by n rates in response to a write command signal, and a second memory ( 7) supplied with the output of the fourth shift circuit (5) and the output of the third shift circuit (4) for storing the pattern address shifted by n rates in response to the write command signal. Data logging can be accomplished without being affected by variable time intervals of write enable strobe pulses.

Claims

1. A data logging apparatus, comprising:

a first shift circuit having inputs supplied with data to be logged and a strobe signal, the first shift circuit shifting said data to be logged by n rates, the shifted data being an output signal of the first shift circuit;

a second shift circuit having an input supplied with a basic clock signal, the second shift circuit shifting said basic clock signal by n rates or alternatively (n-1) rates, the shifted clock signal being an output signal of the second shift circuit and an input to the first shift circuit, the first shift circuit shifting said data under the shifted clock signal;

a write pulse generating circuit having an input supplied with said shifted clock signal of said second shift circuit, the write pulse generating circuit generating as an output signal a write pulse signal;

a third shift circuit having inputs supplied with a memory address signal and the basic clock signal, the third shift circuit shifting the memory address signal by n rates under said basic clock signal, the shifted memory address signal being an output signal of the third shift circuit;

a fourth shift circuit having inputs supplied with a pattern address signal and the basic clock signal, the fourth shift circuit shifting the pattern address signal by n rates under said basic clock signal, the shifted pattern address signal being an output signal of the fourth shift circuit;

a first memory having a data input supplied with said shifted data from said first shift circuit, a write signal input supplied with said write pulse signal from said write pulse generating circuit, and an address input supplied with said shifted memory address signal from said third shift circuit, the first memory storing the shifted data at the shifted memory address in response to the write pulse signal; and

a second memory having a data input supplied with said shifted pattern address signal from said fourth shift circuit, a write signal input supplied with said write pulse signal from said write pulse generating circuit, and an address input supplied with said shifted memory address signal from said third shift circuit, the second memory storing said shifted pattern address at the shifted memory address in response to said write pulse signal.

2. A system for testing a device, comprising:

pattern generating means for generating pattern data to be applied to a device under test and for generating an expected pattern which is expected to be outputted from said device in response to said pattern data applied thereto;

a decision circuit for deciding whether actual pattern data outputted from said device under test coincides with said expected pattern, the decision being an output signal of the decision circuit; and

a data logging apparatus, wherein said data logging apparatus comprises;

a first shift circuit having inputs supplied with the decision signal of said decision circuit and a strobe signal, the first shift circuit shifting said decision signal of said decision circuit by n rates, the shifted decision signal being an output signal of the first shift circuit, where n represents a given integer;

a second shift circuit having an input supplied with a basic clock signal, the second shift circuit shifting said timing of said basic clock signal by n rates, the shifted clock signal being an output signal of the second shift circuit and an input of the first shift circuit, the first shift circuit shifting the decision signal of said decision circuit under the shifted clock signal;

a write pulse generating circuit having an input supplied with said shifted clock signal of said second shift circuit, the write pulse generating circuit generating as an output signal a write pulse signal;

a third shift circuit having inputs supplied with a memory address signal and the basic clock signal, the third shift circuit shifting the memory address signal by n rates under said basic clock signal, the shifted memory address signal being an output signal of the third shift circuit;

a fourth shift circuit having inputs supplied with a pattern address signal and the basic clock signal, the fourth shift circuit shifting the pattern address signal by n rates under said basic clock signal, the shifted pattern address signal being an output signal of the fourth shift circuit;

a first memory having a data input supplied with said shifted decision signal from said first shift circuit, a write signal input supplied with said write pulse signal from said write pulse generating circuit, and an address input supplied with said shifted memory address signal from said third shift circuit, the first memory storing the shifted decision signal at the shifted memory address in response to the write pulse signal; and

a second memory having a data input supplied with said shifted pattern address signal from said fourth shift circuit, a write signal input supplied with said write pulse signal from said write pulse generating circuit, and an address input supplied with said shifted memory address signal from said third shift circuit, the second memory storing said shifted pattern address at the shifted memory address in response to said write pulse signal.