Low-power integrated circuit with selectable battery modes

• US 5,306,961 A
• Filed: 05/08/1992
• Issued: 04/26/1994
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Leo, Robert D.
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US07/882,244
• Time in Patent Office: 718 Days
• Field of Search: 307/296.1, 307/296.3, 307/296.4, 307/350, 307/66, 307/355, 307/362, 365/229
• US Class Current: 327/530
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/047 the record carrier being shaped as a coin or a gambling token
• CPC Class Codes: G06K 19/0706 the battery being replaceable
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G06K 7/0086 the connector comprising a circuit for steering the operations of the card connector
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
• CPC Class Codes: H05K 1/0393 : Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308

Abstract

An integrated circuit which can be operated EITHER in a battery-backed mode OR in a battery-operated mode. This is accomplished without any necessity for bond options, mask alteration, laser writing, or fuse blowing. The integrated circuit of the presently preferred embodiment has one pin BAT for battery input, and another pin VCCI for connection to a system power supply. Two PMOS switches are provided to connect one of these two pins to an on-chip power supply VDD under appropriate conditions. In addition, the disclosed integrated circuit has a third pin which can alternatively be used for battery input. The logic which controls the PMOS switches ensures that they will not turn on if their respective power inputs VCCI or BAT are low.

Claims

1. An integrated circuit, comprising:

first, second, and third power input terminals;

said first input terminal being operatively connected to an internal power supply line;

a ground terminal, for connection to ground;

a comparator,

having a negative input thereof operatively connected to said second terminal, and

having a positive input thereof and a power supply input thereof operatively connected to said third terminal,

said comparator being configured to provide a high logic output when said third terminal is at a higher voltage than said second terminal while said comparator is being powered;

a first power switch, configured to connect said third terminal to said internal power supply line when said output of said comparator is at a high logic state;

a second power switch, configured to connect said second terminal to said internal power supply line when said output of said comparator is at a low logic state and the voltage at said second terminal is at least a high logic level;

whereby, (i) when said integrated circuit is combined with a battery attached to said second or third terminal, and a system power supply attached to the other of said second and third terminals, said chip will operate in a battery-backed mode;

and (ii) when both said second and third terminals are grounded, said integrated circuit will operate in a battery-operated mode, when said first terminal is powered up.

2. The integrated circuit of claim 1, wherein said first power switch is a P-channel insulated gate field effect transistor.

3. The integrated circuit of claim 1, wherein said switch is a P-channel insulated gate field effect transistor.

4. The integrated circuit of claim 1, wherein said first power switch is a P-channel insulated gate field effect transistor with a width to length ratio greater than 2000.

5. The integrated circuit of claim 1, wherein said second power switch is a P-channel insulated gate field effect transistor with a width to length ratio greater than 2000.

6. The integrated circuit of claim 1, wherein said negative input of said comparator is connected to said second terminal through an analog filter stage.

7. The integrated circuit of claim 1, wherein said positive input of said comparator is connected to said third terminal through an analog filter stage.

8. The integrated circuit of claim 1, wherein said positive input of said comparator is connected to said third terminal through an analog filter stage, and said power supply input of said comparator is connected directly to said third terminal without any intervening filter stage.