Binary controlled digital tapped delay line
First Claim
1. A binary-controlled digital tapped delay line having a plurality of stages connected in cascade, each stage comprising:
- differential amplifier means responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair;
first loading means comprising a plurality of load devices interconnected to produce a cumulative loading effect and connected to a input of a first transistor of said differential transistor pair for delaying turn-on of said first transistor;
second loading means comprising a same plurality of load devices also interconnected to produce a cumulative loading effect and connected to an input of a second transistor of said differential transistor pair for delaying turn-on of second transistor, said first loading means and said second loading means each being connected to a first circuit node; and
delay control means responsive to a binary-controlled signal and connected to said first circuit node for causing turn-on of first and second transistors to be delayed a set amount of time when said binary control signal is asserted.
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Accused Products
Abstract
An electronic, binary-controlled digital tapped delay line is realized by a plurality of like stages connected in cascade. Each stage comprises a differential amplifier circuit responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair. A first loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading effect is connected to an input of a first transistor of the differential transistor pair for delaying turn-on of the first transistor. Similarly, a second loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading is connected to an input of a second transistor of the differential transistor pair for delaying turn-on of the second transistor, the first and second loading circuits each being connected to a first circuit node. A delay control circuit is responsive to a binary control signal and connected to the first circuit node for causing turn-on of the first and second transistors to be delayed by a set amount of time when the binary control signal is asserted.
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Citations
8 Claims
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1. A binary-controlled digital tapped delay line having a plurality of stages connected in cascade, each stage comprising:
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differential amplifier means responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair; first loading means comprising a plurality of load devices interconnected to produce a cumulative loading effect and connected to a input of a first transistor of said differential transistor pair for delaying turn-on of said first transistor; second loading means comprising a same plurality of load devices also interconnected to produce a cumulative loading effect and connected to an input of a second transistor of said differential transistor pair for delaying turn-on of second transistor, said first loading means and said second loading means each being connected to a first circuit node; and delay control means responsive to a binary-controlled signal and connected to said first circuit node for causing turn-on of first and second transistors to be delayed a set amount of time when said binary control signal is asserted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification