Phase-and-frequency mode/phase mode detector with the same gain in both modes

• US 5,307,028 A
• Filed: 10/16/1992
• Issued: 04/26/1994
• Est. Priority Date: 10/16/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation
• Inventors: Chen, Dao-Long
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/961,975
• Time in Patent Office: 557 Days
• Field of Search: 331/1 A, 331/10, 331/11, 331/16, 331/25, 331/DIG. 2, 307/510, 307/516, 307/525, 307/526, 307/527, 307/528, 328/133, 328/134, 375/120, 360/51
• US Class Current: 331/1.00A
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A dual-mode detector which has phase-detection and phase-and-frequency-detection modes of operation, each mode of operation having the same gain. The detector includes a detection and feedback circuit for detecting phase and frequency differences, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences. A mode-switching circuit switches the detection and feedback circuit between the phase-detection and the phase-and-frequency-detection modes of operation. A programmable delay circuit delays signals from the mode-switching circuit and provides delayed signals to the detection and feedback circuit. Finally, an optional edge detection circuit converts predetermined data signals to a format recognizable by the detection and feedback circuit.

Claims

1. A dual-mode detector which has a phase-detection mode of operation and a phase-and-frequency-detection mode of operation;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.

2. The dual-mode detector as recited in claim 1, being part of a phase-locked loop circuit having a voltage-controlled oscillator, the dual-mode detector comprising:

first circuit means for detecting phase differences between a first signal and a signal from the voltage-controlled oscillator during the phase-detection mode, for detecting phase and frequency differences between a second signal and the signal from the voltage-controlled oscillator during the phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences; and

second circuit means for switching the first circuit means between the phase-detection and the phase-and-frequency-detection modes of operation.

3. The dual-mode detector as recited in claim 2, wherein the first signal is a data signal and the second signal is a clock signal.

4. The dual-mode detector as recited in claim 3, further comprising:

third circuit means for delaying signals from the second circuit means and for providing delayed signals to the first circuit means.

5. The dual-mode detector as recited in claim 4, wherein the third circuit means is programmable.

6. The dual-mode detector as recited in claim 4, further comprising:

fourth circuit means for converting predetermined data signals to a format recognizable by the first circuit means.

7. The dual-mode detector as recited in claim 2, wherein the first circuit means comprises:

a first NAND gage having first and second inputs and an output, the first input being either the first or second signal;

a second NAND gate having first, second, and third inputs and an output, the first input being the output of the first NAND gate, and the output being the first feedback signal and the second input of the first NAND gate;

a first RS-type flip-flop having an input, a reset, and an output, the input being the output of the first NAND gate, the output being the second input of the second NAND gate, and the reset being the third input of the second NAND gate;

a third NAND gate having first and second inputs and an output, the first input being the output of the voltage-controlled oscillator;

a fourth NAND gage having first, second, and third inputs and an output, the first input being the output of the third NAND gate, and the output being the second feedback signal and the second input of the third NAND gage;

a second RS-type flip-flop having an input, a reset, and an output, the input being the output of the third NAND gate, the output being the second input of the fourth NAND gate, and the reset being the third input of the second and fourth NAND gates; and

an AND gate having first, second, third, and fourth inputs and an output, the first input being the output of the first NAND gate, the second input being the output of the first RS-type flip-flop, the third input being the output of the second RS-type flip-flop, the fourth input being the output of the third NAND gate, and the output being the third input of the second and fourth NAND gates.

8. The dual-mode detector as recited in claim 7, wherein the second circuit means comprises:

a multiplixer having first, second, and mode select inputs and an output, the first input being the first signal, the second input being the second signal, and the output being the first input to the first NAND gate of the first circuit means;

a NAND gate having first and second inputs and an output, the first input being the output of the first NAND gate of the first circuit means, the second input being the output of the third NAND gate of the first circuit means;

a D-type flip-flop having a clock input, a reset, and output, the clock input being the output of the multiplexer, and the reset being the output of the NAND gate;

a first NOR gate having first and second inputs and an output, the first input being the output of the D-type flip-flop, the second input being coupled to the mode select of the multiplexer; and

a second NOR gate having first and second inputs and an output, the first input being the output of the first NOR gate, the second input being coupled between the output of the AND gate of the first circuit means and the third inputs of the second and fourth NAND gates.

9. The dual-mode detector as recited in claim 4, wherein the third circuit means comprises:

a plurality of delay cells coupled in series, each delay cell being controlled by an input voltage signal to the voltage-controller oscillator.

10. The dual-mode detector as recited in claim 9, wherein each delay cell comprises:

an inverter having an input and an output, the input being the input to the delay cell and the output being the output to the delay cell;

a field-effect transistor having gate, drain, and source inputs, the drain input being coupled to the output of the inverter, and the gate being coupled to the input voltage signal to the voltage-controlled oscillator; and

a capacitor having first and second inputs, the first input being coupled to the source of the field-effect transistor, and the second input being coupled to a predetermined voltage.

11. The dual-mode detector as recited in claim 5, wherein the third circuit means comprises:

a plurality of delay cells coupled in series, each delay cell being controlled by an input voltage signal to the voltage-controlled oscillator, and a predetermined number of delay cells having an output; and

a multiplexer having inputs from the predetermined number of delay cells and a select input.

12. The dual-mode detector as recited in claim 11, wherein each delay cell comprises:

an inverter having an input and an output, the input being the input to the delay cell and the output being the output to the delay cell;

a field-effect transistor having gate, drain, and source inputs, the drain input being coupled to the output of the inverter, and the gate being coupled to the input voltage signal to the voltage-controlled oscillator; and

a capacitor having first and second inputs, the first input being coupled to the source of the field-effect transistor, and the second input being coupled to a predetermined voltage.

13. The dual-mode detector as recited in claim 4 wherein the data signal comprises a Modified Frequency Modulation (MFM) encoded data signal.

14. The dual-mode detector as recited in claim 4, wherein the amount of delay comprises one-fourth of a bit cell.

15. The dual-mode detector as recited in claim 6, wherein the fourth circuit means comprises:

an XOR gate having first and second inputs and an output, the first input being the data signal; and

a plurality of inverters coupled in series between the first input and the second input of the XOR gate.

16. In a phase-locked loop circuit having a voltage-controlled oscillator, a dual-mode detector comprising:

first circuit means for detecting phase differences between a data signal and a signal from the voltage-controlled oscillator during a phase-detection mode, for detecting phase and frequency differences between a clock signal and the signal from the voltage-controlled oscillator during a phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences;

second circuit means for causing the first circuit means to switch between the phase-detection and the phase-and-frequency-detection modes of operation; and

third circuit means for delaying signals from the second circuit means and for providing delayed signals to the first circuit means;

wherein the third circuit means is programmable;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.

17. In a phase-locked loop circuit having a voltage-controlled oscillator, a dual-mode detector comprising:

first circuit means for detecting phase differences between a data signal and a signal from the voltage-controlled oscillator during a phase-detection mode, for detecting phase and frequency differences between a clock signal and the signal from the voltage-controlled oscillator during a phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences;

second circuit means for causing the first circuit means to switch between the phase-detection and the phase-and-frequency-detection modes of operation; and

third circuit means for converting predetermined data signals to a format recognizable by the first circuit means;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.

18. In a phase-locked loop circuit having a voltage-controlled oscillator, a dual-mode detector comprising:

first circuit means for detecting phase differences between a data signal and a signal from the voltage-controlled oscillator during a phase-detection mode, for detecting phase and frequency differences between a clock signal and the signal from the voltage-controlled oscillator during a phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences;

second circuit means for causing the first circuit means to switch between the phase-detection and the phase-and-frequency-detection modes of operation;

third circuit means for delaying signals from the second circuit means and for providing delayed signals to the first circuit means; and

fourth circuit means for converting predetermined data signals to a format recognizable by the first circuit means;

wherein the third circuit means is programmable;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.

19. A phase-locked loop circuit comprising:

a dual-mode detector which has phase-detection and phase-and-frequency-detection modes of operation;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.

20. The phase-locked loop circuit as recited in claim 19, further comprising:

a voltage-controlled oscillator having an output signal coupled to the dual-mode detector;

a charge pump coupled to the output of the dual-mode detector; and

a loop filter coupled between the charge pump and the voltage-controlled oscillator.

21. The phase-locked loop circuit as recited in claim 20, wherein the dual-mode detector comprises:

first circuit means for detecting phase differences between a first signal and a signal from the voltage-controlled oscillator during the phase-detection mode, for detecting phase and frequency differences between a second signal and the signal from the voltage-controlled oscillator during the phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences; and

second circuit means for causing the first circuit means to switch between the phase-detection and the phase-and-frequency-detection modes of operation.

22. The phase-locked loop circuit as recited in claim 21, wherein the first signal is a data signal and the second signal is a clock signal.

23. The phase-locked loop circuit as recited in claim 22, wherein the dual-mode detector further comprises:

third circuit means for delaying signals from the second circuit means and for providing delayed signals to the first circuit means.

24. The phase-locked loop circuit as recited in claim 23, further comprising:

a frequency divider for dividing the frequency of the output signal from the voltage-controlled oscillator by a predetermined number and for providing an output signal having the quotient frequency to the first circuit means.

25. The phase-locked loop circuit as recited in claim 24, wherein the third circuit means and the frequency divider are programmable.

26. The phase-locked loop circuit as recited in claim 23, wherein the dual-mode detector further comprises:

fourth circuit means for converting predetermined data signals to a format recognizable by the first circuit means.

27. The phase-locked loop circuit as recited in claim 21, wherein the first circuit means comprises:

a first NAND gate having first and second inputs and an output, the first input being either the first or second signal;

a second NAND gate having first, second, and third inputs and an output, the first input being the output of the first NAND gate, and the output being the first feedback signal and the second input of the first NAND gate;

a first RS-type flip-flop having an input, a reset, and an output, the input being the output of the first NAND gage, the output being the second input of the second NAND gate, and the reset being the third input of the second NAND gate;

a third NAND gate having first and second inputs and an output, the first input being the output of the voltage-controlled oscillator;

a fourth NAND gate having first, second , and third inputs and an output, the first input being the output of the third NAND gate, and the output being the second feedback signal and the second input of the third NAND gate;

a second RS-type flip-flop having an input, a reset, and an output, the input being the output of the third NAND gate, the output being the second input of the fourth NAND gate, and the reset being the third input of the second and fourth NAND gates; and

an AND gate having first, second, third, and fourth inputs and an output, the first input being the output of the first NAND gate, the second input being the output of the first RS-type flip-flop, the third input being the output of the second RS-type flip-flop, the fourth input being the output of the third NAND gate, and the output being the third input of the second and fourth NAND gates.

28. The phase-locked loop circuit as recited in claim 27, wherein the second circuit means comprises:

a multiplexer having first, second, and mode select inputs and an output, the first input being the first signal, the second input being the second signal, and the output being the first input to the first NAND gate of the first circuit means;

a NAND gate having first and second inputs and an output, the first input being the output of the first NAND gate of the first circuit means, the second input being the output of the third NAND gate of the first circuit means;

a D-type flip-flop having a clock input, a reset, and output, the clock input being the output of the multiplexer, and the reset being the output of the NAND gate;

a first NOR gate having first and second inputs and an output, the first input being the output of the D-type flip-flop, the second input being coupled to the mode select of the multiplexer; and

a second NOR gate having first and second inputs and an output, the first input being the output of the first NOR gate, the second input being coupled between the output of the AND gate of the first circuit means and the third inputs of the second and fourth NAND gates.

29. The phase-locked loop circuit as recited in claim 23, wherein the third circuit means comprises:

a plurality of delay cells coupled in series, each delay cell being controlled by an input voltage signal to the voltage-controlled oscillator.

30. The phase-locked loop circuit as recited in claim 29, wherein each delay cell comprises:

an inverter having an input and an output, the input being the input to the delay cell and the output being the output to the delay cell;

a field-effect transistor having gate, drain, and source inputs, the drain input being coupled to the output of the inverter, and the gate being coupled to the input voltage signal to the voltage-controlled oscillator; and

a capacitor having first and second inputs, the first input being coupled to the source of the field-effect transistor, and the second input being coupled to a predetermined voltage.

31. The phase-locked loop circuit as recited in claim 25, wherein the third circuit means comprises:

a plurality of delay cells coupled in series, each delay cell being controlled by an input voltage signal to the voltage-controlled oscillator, and a predetermined number of delay cells having an output; and

a multiplexer having inputs from the predetermined number of delay cells and a select input.

32. The phase-locked loop circuit as recited in claim 31, wherein each delay cell comprises:

an inverter having an input and an output, the input being the input to the delay cell and the output being the output to the delay cell;

a field-effect transistor having gate, drain, and source inputs, the drain input being coupled to the output of the inverter, and the gate being coupled to the input voltage signal to the voltage-controlled oscillator; and

a capacitor having first and second inputs, the first input being coupled to the source of the field-effect transistor, and the second input being coupled to a predetermined voltage.

33. The phase-locked loop circuit as in claim 24 wherein the data signal comprises a Modified Frequency Modulation (MFM) encoded data signal and the predetermined number comprises four.

34. The phase-locked loop circuit as recited in claim 23, wherein the amount of delay comprises one-fourth of a bit cell.

35. The phase-locked loop circuit as recited in claim 26, wherein the fourth circuit means comprises:

an XOR gate having first and second inputs and an output, the first input being the data signal; and

a plurality of inverters coupled in series between the first input and the second input of the XOR gate.

36. A phase-locked loop circuit comprising:

a voltage-controlled oscillator;

a loop filter coupled to the voltage-controlled oscillator;

a charge pump coupled to the loop filter;

a dual-mode detector, coupled between the voltage-controlled oscillator and the charge pump, and which has phase-detection and phase-and-frequency-detection modes of operation, including first circuit means for detecting phase differences between a data signal and a signal from the voltage-controlled oscillator during the phase-detection mode, for detecting phase and frequency differences between a clock signal and the signal from the voltage-controlled oscillator during the phase-and-frequency-detection mode, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences;

second circuit means for causing the first circuit means to switch between the phase-detection and the phase-and-frequency-detection modes of operation;

third circuit means for delaying signals from the second circuit means and for providing delayed signals to the first circuit means; and

a frequency divider for dividing the frequency of the output signal from the voltage-controlled oscillator by a predetermined number and for providing an output signal having the quotient frequency to the first circuit means;

wherein the dual-mode detector has a first gain while in the phase-detection mode and a second gain while in the phase-and-frequency-detection mode; and

wherein the first and second gains are the same.