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High performance static latches with complete single event upset immunity

  • US 5,307,142 A
  • Filed: 11/15/1991
  • Issued: 04/26/1994
  • Est. Priority Date: 11/15/1991
  • Status: Expired due to Fees
First Claim
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1. A bi-stable asymmetric response latch, consisting essentially of:

  • (a) a first and a second inverter, each of said inverters having a p-channel transistor and a n-channel transistor, said inverters cross-coupled so that a source/drain of said n-channel transistor of said first inverter is cross-coupled to a gate of said p-channel transistor of said second inverter at a first coupling node, and a source/drain of said p-channel transistor of said second inverter is cross-coupled to a gate of said n-channel transistor of said first inverter at a second coupling node;

    wherein one of said inverters has a single hardened logic state and the other of said inverters has a soft logic state;

    (b) a first voltage dividing means interposed between said p-channel source/drain of said first inverter and said first cross-coupling node wherein the logic state of said first inverter can only be changed by an ion strike when the voltage level at said first coupling node is low;

    (c) a second voltage dividing means interposed between said second coupling node and a n-channel source/drain of said second inverter wherein the logic state of said second inverter can only be changed by an ion strike when the voltage level at said second coupling node is high.

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