Chiplid, multichip semiconductor package design concept

• US 5,307,240 A
• Filed: 12/02/1992
• Issued: 04/26/1994
• Est. Priority Date: 12/02/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McMahon, John F.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Whang, Young
• Application Number:
  US07/985,209
• Time in Patent Office: 510 Days
• Field of Search: 361/380, 361/392, 361/394, 361/399, 361/400, 361/402, 361/403, 361/418, 361/419, 361/411, 361/420, 361/728, 361/730, 361/752, 361/760, 361/765, 361/767, 361/808, 361/809 , 361/810, 174/52.2, 174/52.3, 174/52.4, 174/255, 174/256, 174/259, 257/678, 257/686, 257/690, 257/692, 439/69, 439/74
• US Class Current: 361/728
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 Monolayer substrate
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An electronic package assembly which has a first electrical device mounted to a housing and a second electrical device attached to the lid of the package. The first and second devices are completely encapsulated by the lid and housing, and are typically coupled to a printed circuit board by pads on the bottom surface of the package. The electrical devices may be active or passive elements that are coupled together by conductive pads located on the top and bottom surfaces of the housing and lid, respectively. The conductive pads are typically soldered together when the lid is attached to the housing.

Claims

1. An electronic package assembly, comprising:

a housing having a first cavity and a plurality of first conductive pads located on a top surface of said housing;

a first electrical device attached to said housing within said first cavity and coupled to said first conductive pads;

a lid attached to said housing so that said fist cavity is encapsulated by said lid and housing, said lid further having a plurality of second conductive pads on a bottom surface of said lid;

a second electrical device attached to said lid and encapsulated by said housing and said lid; and

,

a plurality of conductive vias coupled to said first and second pads and encapsulated by a dielectric material which seals said lid to said housing.

2. The assembly as recited in claim 1, wherein said first electrical device is coupled to said second electrical device through said conductive pads.

3. The assembly as recited in claim 1, wherein said dielectric material has liquid transition temperature that is approximately equal to a reflow temperature of a solder.

4. The assembly as recited in claim 1, wherein said second electrical device is located in a second cavity in said lid.

5. A method for assembling an electronic package assembly, comprising the steps of:

a) providing a housing that has a first electrical device located in a first cavity within said housing, said housing further having a plurality of first conductive pads on a top surface of said housing;

b) providing a lid that has a second electrical device and a plurality of second conductive pads on a bottom surface of said lid;

c) applying solder preform material to said second conductive pads;

d) placing said housing onto said lid such that said first conductive pads are adjacent to said second conductive pads;

d) apply a dielectric material to said lid in a manner to encircle said solder preform material;

f) heating said housing and lid until said solder and said dielectric material reflow to a liquid state; and

g) cooling said housing and lid such that said reflowed solder solidifies and attaches said first and second conductive pads and said dielectric solidifies to seal said lid to said housing.