Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

• US 5,307,315 A
• Filed: 05/31/1991
• Issued: 04/26/1994
• Est. Priority Date: 06/01/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takashima, Daisaburo, Ohta, Masako, Oowaki, Yukihito
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): DINH, TAN X
• Application Number:
  US07/708,362
• Time in Patent Office: 1,061 Days
• Field of Search: 365/189.09, 365/230.06, 307/296.1, 307/296.6, 307/296.8
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Abstract

A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.

Claims

1. An integrated circuit for use with an array of rows and columns of memory cells associated with bit lines and word lines on a substrate, said circuit comprising:

first voltage generator means for providing a selected one of said word lines with a word-line drive voltage that is potentially high enough to enable write of a digital information of high level;

second voltage generator means connected to said first voltage generator means, for receiving a power supply voltage, and for generating a voltage of a fixed potential which is essentially insensitive to a potential variation in the power supply voltage;

said first voltage generator means generating the drive voltage by performing a capacitive carrier storage using said voltage of fixed potential; and

said second voltage generator means comprising compensator circuit means arranged on said substrate, for individually determining the potential level of the reference voltage, in accordance with resultant physical conditions of actually manufactured memory cells of said semiconductor memory device so as to compensate for potential variations is the work-line drive voltage which may take place due to variations in the physical conditions of the memory cells, and for causing the determined potential level of said reference voltage to be substantially constant or less in gradient than a high level voltage to be applied to said bit lines in an allowable range of the power supply voltage.

2. A circuit according to claim 1, wherein said first voltage generator means comprises:

capacitor means for storing carriers therein when said voltage of fixed level is applied thereto.

3. A circuit according to claim 2, wherein said second voltage generator means comprises:

a first reference voltage generation circuit connected to said power supply voltage, for generating a first d.c. reference voltage;

a second reference voltage generation circuit connected to said power supply voltage, for generating

a second d.c. reference voltage; and

said capacitor means having a first electrode to which the first reference voltage is applied, and a second electrode to which the second reference voltage is applied.

4. A circuit according to claim 3, wherein at least one of said first and second reference voltage generation circuits includes at least one diode-connected metal-insulator-semiconductor transistor.

5. A circuit according to claim 3, wherein at least one of said first and second reference voltage generation circuits includes a series circuit of diode-connected metal-insulator-semiconductor transistors.

6. A circuit according to claim 5, wherein said at least one of said first and second reference voltage generation circuits includes an amplifier connected to said series circuit of diode-connected metal-insulator-semiconductor transistors.

7. A circuit according to claim 1, wherein said compensator circuit means determines the potential level of the reference voltage so as to compensate for a variation in dielectric breakdown voltages of said actually manufactures memory cells.

8. A circuit according to claim 7, wherein said compensator means generates a constant voltage that is independent from variation in the power supply voltage when said power supply voltage is potentially smaller in magnitude than a predetermined level, and, when the power supply voltage is higher than said predetermined level, generates a varying voltage which is substantially proportional to a dielectric breakdown level of cell transistors included in the memory cells associated with a currently selected word line.

9. A circuit according to claim 8, wherein said varying voltage is potentially proportional to thickness of gate insulation layers of said cell transistors.

10. A circuit according to claim 1, further comprising:

additional circuit means for detecting a current leakage component inherent in the selected word line, and for selectively generating a voltage that compensates for the current leakage component thus detected.

11. A circuit according to claim 10, wherein said additional circuit means comprises:

comparator means for receiving an actual voltage on said selected word line, for receiving an externally supplied reference voltage indicative of a suitable potential level on said selected word line, and for comparing these voltage with each other to generate an comparison output;

oscillator means for selectively performing an oscillation responding to the comparison output; and

charger means for operating in response to an output of said oscillator means, and for generating a compensated word-line drive voltage.

12. A circuit according to claim 8, further comprising:

means for receiving the power supply voltage externally and for producing an internal power supply voltage that is replaced with said power supply voltage.