Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage
First Claim
1. An integrated circuit for use with an array of rows and columns of memory cells associated with bit lines and word lines on a substrate, said circuit comprising:
- first voltage generator means for providing a selected one of said word lines with a word-line drive voltage that is potentially high enough to enable write of a digital information of high level;
second voltage generator means connected to said first voltage generator means, for receiving a power supply voltage, and for generating a voltage of a fixed potential which is essentially insensitive to a potential variation in the power supply voltage;
said first voltage generator means generating the drive voltage by performing a capacitive carrier storage using said voltage of fixed potential; and
said second voltage generator means comprising compensator circuit means arranged on said substrate, for individually determining the potential level of the reference voltage, in accordance with resultant physical conditions of actually manufactured memory cells of said semiconductor memory device so as to compensate for potential variations is the work-line drive voltage which may take place due to variations in the physical conditions of the memory cells, and for causing the determined potential level of said reference voltage to be substantially constant or less in gradient than a high level voltage to be applied to said bit lines in an allowable range of the power supply voltage.
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Accused Products
Abstract
A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.
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Citations
12 Claims
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1. An integrated circuit for use with an array of rows and columns of memory cells associated with bit lines and word lines on a substrate, said circuit comprising:
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first voltage generator means for providing a selected one of said word lines with a word-line drive voltage that is potentially high enough to enable write of a digital information of high level; second voltage generator means connected to said first voltage generator means, for receiving a power supply voltage, and for generating a voltage of a fixed potential which is essentially insensitive to a potential variation in the power supply voltage; said first voltage generator means generating the drive voltage by performing a capacitive carrier storage using said voltage of fixed potential; and said second voltage generator means comprising compensator circuit means arranged on said substrate, for individually determining the potential level of the reference voltage, in accordance with resultant physical conditions of actually manufactured memory cells of said semiconductor memory device so as to compensate for potential variations is the work-line drive voltage which may take place due to variations in the physical conditions of the memory cells, and for causing the determined potential level of said reference voltage to be substantially constant or less in gradient than a high level voltage to be applied to said bit lines in an allowable range of the power supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification