Apparatus and method for fault detection on redundant signal lines via encryption

• US 5,307,409 A
• Filed: 12/22/1992
• Issued: 04/26/1994
• Est. Priority Date: 12/22/1992
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Driscoll, Kevin R.
• Primary Examiner(s): Cain, David C.
• Application Number:
  US07/995,107
• Time in Patent Office: 490 Days
• Field of Search: 380/2, 380/42
• US Class Current: 380/2
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1625 in communications, e.g. transmission, interfaces
• CPC Class Codes: H04L 9/004 for fault attacks
• CPC Class Codes: H04L 9/08 Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords network architectures or network communication protocols for supporting key management in a packet data network H04L63/06
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

A fault detection apparatus and method combines each of a plurality of redundant digital data signals with a unique key signal for transmission over one of a plurality of signal lines and recombines each with its unique key signal at a receiving end. The recombined signals are then compared at the receiving end to detect certain faults between or among the plurality of what should be identical received signals.

Claims

1. A fault detection apparatus for use in transmitting a first set of multiple redundant digital data signals over a plurality of signal lines comprising:

a plurality of sending exclusive OR gate means, each for receiving as inputs one of said first set of multiple redundant digital data signals and a unique key signal corresponding to one of said plurality of signal lines, the output of each of which is coupled to said one of said plurality of signal lines;

a plurality of receiving exclusive OR gate means, each of which is coupled to one of said plurality of signal lines and is for receiving as inputs the signal on said one of said plurality of signal lines and said unique key signal corresponding to said one of said signal lines; and

comparison means for comparing the outputs of said receiving exclusive OR gate means.

2. A fault detection apparatus in accordance with claim 1 for four signal lines wherein said unique key signals comprise a first key signal which is a steady state logical zero, a second key signal which is an alternating zero and one bit pattern of constant frequency, a third key signal which is a steady state logical one, and a fourth key signal which is the inverse of said second key signal.

3. A fault detection apparatus in accordance with claim 1 wherein said key signals are selected to produce data signals on said signal lines having a nearly constant DC power level.

4. A fault detection apparatus in accordance with claim 1 wherein said key signals are selected to produce data signals on said signal lines having a nearly constant AC power level.

13. A fault detection apparatus in accordance with claim 1 for additionally transmitting a second set of multiple redundant digital signals over said plurality of signal lines further comprising:

an additional plurality of sending exclusive OR gate means, each for receiving as inputs one of said second set of multiple redundant digital data signals and a unique key signal corresponding to one of said plurality of signal lines, the output of each of which is coupled to said one of said plurality of signal lines.

5. In a system for transmitting a plurality of identical redundant digital data signals over a plurality of signal lines, a method for fault detection comprising the steps of:

combining each of said identical redundant digital signals with a unique key signal in a combining means to form an encrypted digital data signal,

transmitting each of said encrypted digital data signals over one of said plurality of signal lines,

recombining each of said encrypted digital data signals with its corresponding unique key signal in a recombining means to produce a decrypted digital data signal; and

comparing said decrypted digital data signals to detect faults where all of said decrypted digital signals are identical absent a fault.

6. The method of claim 5 wherein said combining means and said recombining means comprise exclusive OR gate means.

7. The method of claim 6 wherein said key signals are selected to result in a nearly constant DC power level for the average of said encrypted digital signals.

8. The method of claim 6 wherein said key signals are selected to result in a nearly constant AC power level for the average of said encrypted digital signals.

9. A fault detection apparatus for transmitting first, second, third and fourth identical digital data signals over first, second, third and fourth respective signal lines comprising:

first sending exclusive OR gate means for receiving said first digital data signal and a first key signal, the output of which is coupled to said first signal line;

first receiving exclusive OR gate means, coupled to said first signal line, for receiving as inputs the signal on said first signal line and said first key signal;

second sending exclusive OR gate means for receiving said second digital data signal and a second key signal, the output of which is coupled to said second signal line;

second receiving exclusive OR gate means, coupled to said second signal line, for receiving as inputs the signal on said second signal line and said second key signal;

third sending exclusive OR gate means for receiving said third digital data signal and a third key signal, the output of which is coupled to said third signal line;

third receiving exclusive OR gate means, coupled to said third signal line, for receiving as inputs the signal on said third signal line and said third key signal;

fourth sending exclusive OR gate means for receiving said fourth digital data signal and a fourth key signal, the output of which is coupled to said fourth signal line;

fourth receiving exclusive OR gate means, coupled to said fourth signal line, for receiving as inputs the signal on said fourth signal line and said fourth key signal; and

comparison means, coupled to the outputs of said first, second, third and fourth receiving exclusive OR gate means, for comparing the outputs of said first, second, third and fourth receiving exclusive OR gate means.

10. The apparatus of claim 9 wherein said first key signal is a constant logical zero, said second key signal is an alternating logical zero and logical one pattern of constant frequency, said third key signal is a constant logical one, and said fourth key signal is the inverse of said second key signal.

11. The apparatus of claim 9 wherein said first, second, third, and fourth key signals are selected to provide an average of the signals on said first, second, third and fourth signal lines having a constant DC power level.

12. The apparatus of claim 9 wherein said first, second, third and fourth key signals are selected to provide an average of the signals on said first, second, third and fourth signal lines having a constant AC power level.