Apparatus and method for processing literal operand computer instructions

• US 5,307,474 A
• Filed: 05/11/1992
• Issued: 04/26/1994
• Est. Priority Date: 09/30/1987
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Korematsu, Jiro, Sakamura, Ken
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Elmore, Reba I.
• Application Number:
  US07/882,743
• Time in Patent Office: 715 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400 MS, 395/425 MS
• US Class Current: 712/210
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A data processor of this invention capable of extending the expressible range of constant data in which a portion of the expressible range not necessary for an instruction is removed from that range and the vacancy thus made is utilized for extending the range of data necessary for the instruction.

Claims

1. In a computer having an ALU and an instruction register, apparatus for processing a plurality of computer instructions stored in a computer memory, including at least a first computer instruction and a second computer instruction said first computer instruction and said second computer instruction both being part of said plurality of computer instructions, said first computer instruction having an operation code and at least a first field for holding a literal operand having a binary value, said literal operand which is held in said first field in said first computer instruction being a first of a plurality of kinds of literal operands, each of said plurality of kinds of literal operands having a range of permissible values different from the range of all others of said plurality of kinds of literal operands said second computer instruction having an operation code and at least a first field for holding a literal operand having a binary value, said literal operand which is held in said first field in said second computer instruction being a second of said plurality of kinds of literal operands the contents of said first field of said first computer instruction being identical to the contents of said first field of said second computer instruction, the operation code of said second computer instruction being different from the operation code of said first computer instruction, the apparatus comprising:

an instruction decoding means for sequentially receiving said first computer instruction and said second computer instruction and sequentially outputting to a first signal line for control of a literal operand extension, a first signal indicating the kind of literal operand held in said first field of said first instruction and a second signal indicating the kind of literal operand held in said first field of said second instruction;

literal operand extension means, coupled to said instruction decoding means, to sequentially receive said first and second signals from said instruction decoding means and coupled to the instruction register to sequentially receive contents of said first literal operand field obtained from said first computer instruction and said first literal operand field obtained from said second computer instruction, said literal operand extension means being a means for selectively changing the values of said received first and second literal operand fields and sequentially outputting a first and second extended operand to a second signal line, said first extended operand being output in response to said first signal and said contents of said first literal operand field obtained from said first instruction having a first operation code, said first extended operand being different from said second extended operand;

said first and second extended operands being output by said literal operand extension means for receipt by the ALU for execution of said first instruction operating on said first extended literal operand and for execution of said second instruction operating on said second extended literal operand; and

means, coupled to said literal operand extension means, for transferring contents of said first field of said first computer instruction to said literal extension means when said first computer instruction is transferred into said instruction decode unit, for extension of the contents of said literal operand field.

2. Apparatus, as claimed in claim 1, wherein said literal extension means includes means for receiving contents of a third literal operand field after receiving said contents of said first literal operand field obtained from said first computer instruction and said second literal operand field obtained from said second computer instruction, and outputting a third extended operand to said second signal line, said first extended operand being different from said third extended operand, said contents of said third literal operand field being identical to the contents of said first field in said first computer instruction and the contents of said first field in said second computer instruction, said third literal operand field being part of a third instruction having a third operation code, said third operation code being different from said first and second operation codes.

3. Apparatus, as claimed in claim 1, wherein said first field has a width of N bits wherein N is greater than zero and wherein said extended operands have values within one of first, second, third and fourth ranges of values,

said first range of values being from 0 to 2^N -1,

said second range of values being from 1 to 2^N,

said third range of values being from -1 to -2^N, and

said fourth range of values being from 0 to 2×

(2N-1).

4. Apparatus, as claimed in claim 1, wherein said literal extension means includes means for combining at least said first signal and said literal operand which is held in said first field in said first computer instruction to provide said first extended operand.

5. In a computer having an ALU, a method for processing computer instructions having at least an operation code and a first field said first field being a field for holding a binary literal operand having a first bit width of N bits whereby the range of values which can be expressed by said binary literal operand is 0 to (2^N -1),the method comprising:

providing first means for receiving contents of a literal operand field and outputting an extended operand;

transferring contents of a literal operand field of a first instruction to said first means;

transferring a first control signal to said first means; and

combining said first signal with said contents of said literal operand field of said first instruction, using said first means, to produce a first extended operand for receipt by the ALU for execution of said first instruction, said first instruction being an instruction for operating on said first extended operand, said first extended operand having one of a plurality of possible values, wherein the range of said plurality of possible values is different from 0 to (2^N -1);

transferring contents of a literal operand field of a second instruction to said first means, said contents of said literal operand field of said second instruction being identical to said contents of said literal operand field of said first instruction;

transferring a second control signal to said first means, wherein said second signal is different from said first signal; and

combining said second signal with said contents of said literal operand field of said second instruction, using said first means to produce a second extended operand, different from said first extended operand;

transferring said second extended operand to the ALU for execution of said second instruction, said second instruction being an instruction for operating on said second extended operand.

6. In a computer having a storage means storing a plurality of instructions, each of said plurality of instructions including an operation code, said plurality of instructions including at least a first instruction and a second instruction, said first instruction including at least a first field for holding a literal operand, said literal operand held in said first field in said first instruction having an effective range and said literal operand held in said first field in said first instruction being a first of a plurality of kinds of literal operands, said second instruction including at least a first field for holding a literal operand, said literal operand held in said first field of said second instruction having an effective range and said literal operand held in said first field in said second instruction being a second of said plurality of kinds of literal operands each of said plurality of kinds of literal operands having a range of permissible values different from the range of all others of said plurality of kinds of literal operands, apparatus for extending said effective range of at least said literal operand held in said first field of said first instruction and said literal operand held in said first field of said second instruction comprising:

signal lines for inputting N instruction bits representing a literal operand input from said first instruction;

means for interpreting said operation code of said first instruction and outputting a plurality of type signals indicating said first of said plurality of kinds of literal operands;

means, coupled to said means for interpreting and outputting, for combining said type signals to provide at least a first output signal;

means, coupled to said signal lines and said means for combining said type signals, for combining each of said N instruction bits with at least said first output signal to provide N bits of a literal operand output;

means, coupled to said signal lines and said means for interpreting and outputting, for combining at least a first of said type signals with said N instruction bits to provide a second output signal; and

means for combining said second output signal with a second of said type signals to provide a N+1st bit of said literal operand output.