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Apparatus and method for processing literal operand computer instructions

  • US 5,307,474 A
  • Filed: 05/11/1992
  • Issued: 04/26/1994
  • Est. Priority Date: 09/30/1987
  • Status: Expired due to Fees
First Claim
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1. In a computer having an ALU and an instruction register, apparatus for processing a plurality of computer instructions stored in a computer memory, including at least a first computer instruction and a second computer instruction said first computer instruction and said second computer instruction both being part of said plurality of computer instructions, said first computer instruction having an operation code and at least a first field for holding a literal operand having a binary value, said literal operand which is held in said first field in said first computer instruction being a first of a plurality of kinds of literal operands, each of said plurality of kinds of literal operands having a range of permissible values different from the range of all others of said plurality of kinds of literal operands said second computer instruction having an operation code and at least a first field for holding a literal operand having a binary value, said literal operand which is held in said first field in said second computer instruction being a second of said plurality of kinds of literal operands the contents of said first field of said first computer instruction being identical to the contents of said first field of said second computer instruction, the operation code of said second computer instruction being different from the operation code of said first computer instruction, the apparatus comprising:

  • an instruction decoding means for sequentially receiving said first computer instruction and said second computer instruction and sequentially outputting to a first signal line for control of a literal operand extension, a first signal indicating the kind of literal operand held in said first field of said first instruction and a second signal indicating the kind of literal operand held in said first field of said second instruction;

    literal operand extension means, coupled to said instruction decoding means, to sequentially receive said first and second signals from said instruction decoding means and coupled to the instruction register to sequentially receive contents of said first literal operand field obtained from said first computer instruction and said first literal operand field obtained from said second computer instruction, said literal operand extension means being a means for selectively changing the values of said received first and second literal operand fields and sequentially outputting a first and second extended operand to a second signal line, said first extended operand being output in response to said first signal and said contents of said first literal operand field obtained from said first instruction having a first operation code, said first extended operand being different from said second extended operand;

    said first and second extended operands being output by said literal operand extension means for receipt by the ALU for execution of said first instruction operating on said first extended literal operand and for execution of said second instruction operating on said second extended literal operand; and

    means, coupled to said literal operand extension means, for transferring contents of said first field of said first computer instruction to said literal extension means when said first computer instruction is transferred into said instruction decode unit, for extension of the contents of said literal operand field.

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