Rapid reprogramming terminal

• US 5,307,505 A
• Filed: 05/05/1992
• Issued: 04/26/1994
• Est. Priority Date: 05/05/1992
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Brown, George B., Houlberg, Christian L.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DARBE, VALERIE A
• Application Number:
  US07/878,704
• Time in Patent Office: 721 Days
• Field of Search: 370/85.13, 364/423, 395/800
• US Class Current: 709/253
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 8/61 Installation

Abstract

A rapid reprogramming terminal (RRT) adapted for communication with military aircraft MIL-STD-1553 multiplex data bus which includes generally four avionics and one electronic warfare bus on board each aircraft. The RRT may be used to reprogram all electronic warfare and avionics systems aboard and aircraft including the bus controllers for each avionics or electronic warfare bus and the remote terminals connected to each bus. The RRT includes a high speed digital signal processor which executes functions required to reprogram a remote terminal or bus controller through software stored in an electrically erasable programmable read only memory (EEPROM). The information required to reprogram a remote terminal or bus controller is stored on an IC memory card which is electrically coupled to the digital signal processor. When the RRT establishes communications with either an avionics bus or electronic warfare bus, the digital data required to reprogram, for example, a remote terminal is transferred from the IC memory card through the digital signal processor in a serial format to an encoder/decoder which converts the digital data to Manchester encoded differential data for transfer via the MIL-STD-1553 multiplex data bus to the remote terminal or bus controller being reprogrammed. The present invention also provides for a verify operation whereby the data stored in the IC memory card is compared with the data in the bus controller or remote terminal being reprogrammed to verify that the data is identical.

Claims

1. An apparatus for reprogramming a plurality of remote terminals and a plurality of bus controllers connected to a first communications bus, said first communications bus being a command/response time division multiplex data bus, said reprogramming apparatus being adapated to interface with a second communications bus, said reprogramming apparatus comprising:

an integrated circuit memory card;

first transceiver means for receiving data from said second communications bus or transmitting data to said second communications bus, said first transceiver means formatting the data received thereby to a digital format, the data received from said second communications bus being used to reprogram said remote terminals and said bus controllers connected to said first communications bus;

digital signal processor means for providing a plurality of data transfer control signals, a plurality of address signals, a plurality of enable signals and a plurality of data bytes;

said digital signal processor means having direct access to said integrated circuit memory card such that data to or from said second communications bus is transferred between said integrated circuit memory card and said second communications bus via said first transceiver means and said digital signal processor means and data to or from said first communications bus is transferred between said integrated circuit memory card and said first communications bus via said digital signal processor means;

programmable array logic means for receiving said plurality of data transfer control signals and for decoding said data transfer control signals so as to control the transfer of said data between said second communications bus and said integrated circuit memory card, said integrated circuit memory card being adapted to store said data therein;

said programmable array logic means upon decoding said data transfer control signals generating at least one read signal and at least one write signal;

memory means electrically coupled to said digital signal processor means, said memory means containing software for said digital signal processor means, said software controlling the handling and interpretation of data to and from said first and second communications buses by enabling the operation of said digital signal processor means to accommodate the use of said digital signal processor means with the bus standards, data protocols and formats of said first and second communications buses;

programmable interface means for receiving said address signals, said enable signals and said data bytes from said digital signal processor means and for receiving said read signal and said write signal from said programmable array logic means;

said programmable interface means in response to said address signals, said enable signals, said data bytes and said read and write signals selectively enabling either one of said remote terminals or one of said bus controllers for reprogramming so as to allow said digital signal processor means to control the transfer of reprogramming data from said integrated circuit memory card to said remote terminal or said bus controller being reprogrammed; and

means for providing an interface between said digital signal processor means and said first communications bus, said interface means being adapted to format the reprogramming data being supplied to said remote terminal or said bus controller being reprogrammed in accordance with the bus standards, data protocols and formats of said first communications bus.

2. The reprogramming apparatus of claim 1 wherein said first communications bus is a Military Standard 1553 multiplex data bus.

3. The reprogramming apparatus of claim 1 wherein said second communications bus is an RS-232 communications bus.

4. The reprogramming apparatus of claim 1 wherein said memory means comprises an electrically eraseable read only memory.

5. The reprogramming apparatus of claim 1 wherein said means for providing an interface between said digital signal processor means and said first communications bus comprises:

means for encoding said reprogramming data from said integrated circuit memory card so as to provide Manchester encoded data and for decoding Manchester encoded data from said first communications bus so as to provide digital data, said encoding/decoding means providing an interface between said digital signal processor and said first communications bus;

second transceiver means for transmitting the Manchester encoded data provided by said encoding/decoding means to said first communications bus and for receiving from said first communications bus Manchester encoded data for decoding to said digital format by said encoding/decoding means; and

transformer means for electrically isolating said first communications bus from said digital signal processing means.

6. The reprogramming apparatus of claim 1 wherein said programmable interface means comprises:

first, second and third programmable peripheral interfaces, each of said programmable peripheral interfaces being electrically coupled to said digital signal processor means and said programmable array logic means so as to receive from said digital signal processor means said address signals, enable signals and said data bytes and to receive from said programmable array logic means said read signal and said write signal, each of said programmable peripheral interfaces being enabled by one of said enable signals; and

each of said programmable interfaces having first, second and third eight bit output ports, said address signals controlling the selection of the output port to be enabled and said read and write signals enabling the selected output port;

said first, second and third programmable interfaces providing at each enabled output thereof between one and eight discrete logic signals in response to one of said data bytes;

said discrete logic signals when supplied to said first communications bus selectively enabling one of said remote terminals or one of said bus controllers for reprogramming so as to allow said selected remote terminal or said selected bus controller to be reprogrammed by said reprogramming apparatus.

7. The reprogramming apparatus of claim 1 wherein said bus controller being reprogrammed comprises an AN/ALR-67 Radar Warning Receiver.

8. The reprogramming apparatus of claim 1 wherein said remote terminal being reprogrammed comprises an AN/ALQ-126B Defensive Electronic Counter Measures Set.

13. The reprogramming apparatus of claim 1 wherein said bus controller being reprogrammed comprises an AN/ALR-67 Radar Warning Receiver.

14. The reprogramming apparatus of claim 1 wherein said remote terminal being reprogrammed comprises an AN/ALQ-126B Defensive Electronic Counter Measures Set.

9. An apparatus for reprogramming a plurality of remote terminals and a plurality of bus controllers connected to a first communications bus, said first communications bus being a command/response time division multiplex data bus, said reprogramming apparatus being adapted to interface with a second communications bus, said reprogramming apparatus comprising:

an integrated circuit memory card;

first transceiver means for receiving data from said second communications bus or transmitting data to said second communications bus, said first transceiver means formatting the data received thereby to a digital format, the data received from said second communications bus being used to reprogram said remote terminals and said bus controllers connected to said first communications bus;

digital signal processor means for providing a plurality of data transfer control signals, a plurality of address signals, a plurality of enable signals and a plurality of data bytes;

said digital signal processor means having direct access to said integrated circuit memory card such that data to or from said second communications bus is transferred between said integrated circuit memory card and said second communications bus via said first transceiver means and said digital signal processor means and data to or from said first communications bus is transferred between said integrated circuit memory card and said first communications bus via said digital signal processor means;

programmable array logic means for receiving said plurality of data transfer control signals and for decoding said data transfer control signals so as to control the transfer of said data between said second communications bus and said integrated circuit memory card, said integrated circuit memory card being adapted to store said data therein;

said programmable array logic means upon decoding said data transfer control signals generating at least one read signal and at least one write signal;

memory means electrically coupled to said digital signal processor means, said memory means containing software for said digital signal processor means, said software controlling the handling and interpretation of data to and from said first and second communications buses by enabling the operation of said digital signal processor means to accommodate the use of said digital signal processor means with the bus standards, data protocols and formats of said first and second communications buses;

first, second and third programmable peripheral interfaces, each of said programmable peripheral interfaces being electrically coupled to said digital signal processor means and said programmable array logic means so as to receive from said digital signal processor means said address signals, enable signals and said data bytes and to receive from said programmable array logic means said read signal and said write signal, each of said programmable peripheral interfaces being enabled by one of said enable signals;

each of said programmable interfaces having first, second and third eight bit output ports, said address signals controlling the selection of the output port to be enabled and said read and write signals enabling the selected output port;

said first, second and third programmable interfaces providing at each enabled output thereof between one and eight discrete logic signals in response to one of said data bytes;

said discrete logic signals when supplied to said first communications bus selectively enabling one of said remote terminals or one of said bus controllers for reprogramming so as to allow said selected remote terminal or said selected bus controller to be reprogrammed by said reprogramming apparatus;

means for encoding said reprogramming data from said integrated circuit memory card so as to provide Manchester encoded data and for decoding Manchester encoded data from said first communications bus so as to provide digital data, said encoding/decoding means providing an interface between said digital signal processor and said first communications bus;

second transceiver means for transmitting the Manchester encoded data provided by said encoding/decoding means to said first communications bus and for receiving from said first communications bus Manchester encoded data for decoding to digital format by said encoding/decoding means; and

transformer means for electrically isolating said first communications bus from said digital signal processing means.

10. The reprogramming apparatus of claim 9 wherein said first communications bus is a Military Standard 1553 multiplex data bus.

11. The reprogramming apparatus of claim 9 wherein said second communications bus is an RS-232 communications bus.

12. The reprogramming apparatus of claim 9 wherein said memory means comprises an electrically eraseable read only memory.