Method of formation of transistor and logic gates

• US 5,308,778 A
• Filed: 01/11/1993
• Issued: 05/03/1994
• Est. Priority Date: 03/02/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E., Mazure, Carlos A., Fitch, Jon T.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/003,813
• Time in Patent Office: 477 Days
• Field of Search: 437/48, 437/51, 437/56, 437/57, 437/83, 437/84, 437/89, 437/915, 437/40
• US Class Current: 438/128
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with multiple inputs.

Claims

1. A method for forming at least one transistor, comprising the steps of:

providing a base layer having a surface;

forming a first dielectric layer overlying the base layer;

forming a control electrode conductive layer overlying the first dielectric layer;

forming a second dielectric layer overlying the control electrode conductive layer;

removing portions of each of the first dielectric layer, the control electrode conductive layer, and second dielectric layer to form an opening which exposes the surface of the base layer and to form N control electrodes from the control electrode conductive layer, where N is an integer, each of the N control electrodes having a sidewall;

forming a sidewall dielectric laterally adjacent each sidewall of the N control electrodes; and

forming a conductive region within the opening, the conductive region having a first portion which functions as a first current electrode, the first portion being laterally adjacent the first dielectric layer and overlying the base layer, the conductive region having a second portion functioning as a channel region, the second portion being laterally adjacent each sidewall dielectric of the N control electrodes, and overlying the first current electrodes, and the conductive region having a third portion functioning as a second current electrode, the third portion being laterally adjacent the second dielectric layer and overlying the channel region.

2. The method of claim 1 further comprising the step of:

forming a plurality of M stacked transistors, where M is an integer greater than one, each of the M stacked transistors being formed in accordance with claim 1 and having a predetermined conductivity type that may be different between the M stacked transistors, each of the M stacked transistors having N control electrodes where N is an integer greater than zero and may be different for each of the M stacked transistors, each of the M stacked transistors, except an Mth transistor which overlies all other transistors, having a second current electrode thereof electrically connected to a first current electrode of an immediately overlying transistor.

3. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor and having a first and a second control electrode wherein N is two for the first transistor, and the second transistor having a third control electrode where N is one for the second transistor;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the second transistor to a power supply terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor;

electrically coupling the first control electrode of the first transistor to a first input conductor; and

electrically coupling the second control electrode of the first transistor to a second input conductor to complete formation of a NOR logic gate.

4. The method of claim 2 further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, and each of the first, second, and third transistors having a single control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the third transistor to a power supply terminal;

electrically coupling either a second current electrode of the second transistor or a first current electrode of the third transistor to an output conductor;

electrically coupling a control electrode of the first transistor to a first input conductor; and

electrically coupling a control electrode of the second transistor to a second input conductor to complete formation of a NAND logic gate.

5. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, and each of the first and second transistors having a single control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the second transistor to a power supply terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor; and

electrically coupling the control electrode of the first transistor to an input conductor to complete formation of an inverter logic gate.

6. The method of claim 2 further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, the first transistor having a first and a second control electrode where N is two, and the second and third transistors each having a control electrode;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the third transistor to a power supply terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor;

electrically coupling the first control electrode of the first transistor to a first input conductor;

electrically coupling the second control electrode of the first transistor to a second input conductor; and

electrically coupling either the first input conductor to the control electrode of the third transistor and the second input conductor to the control electrode of the second transistor or coupling the second input conductor to the control electrode of the third transistor and the first input conductor to the control electrode of the second transistor to complete formation of a NOR logic gate.

7. The method of claim 2 further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, each of the first and second transistors having a control electrode where N is one for the first and second transistors, and the third transistor having a first and second control electrode where N is two for the third transistor;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the third transistor to a power supply terminal;

electrically coupling either a second current electrode of the second transistor or a first current electrode of the third transistor to an output conductor;

electrically coupling the first control electrode of the third transistor to a first input conductor;

electrically coupling the second control electrode of the third transistor to a second input conductor; and

electrically coupling either the first input conductor to the control electrode of the first transistor and the second input conductor to the control electrode of the second transistor or coupling the second input conductor to the control electrode of the first transistor and the first input conductor to the control electrode of the second transistor to complete formation of a NAND logic gate.

8. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, and each of the first and second transistors having a control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a reference voltage terminal;

electrically coupling a second current electrode of the second transistor to a power supply terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor; and

electrically coupling the control electrodes of the first and second transistors to a input conductor to complete formation of an inverter logic gate.

9. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor having a first and a second control electrode where N is two for the second transistor, and the first transistor having a control electrode where N is one for the first transistor;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling a second current electrode of the second transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor;

electrically coupling the first control electrode of the second transistor to a first input conductor; and

electrically coupling the second control electrode of the second transistor to a second input conductor to complete formation of a NOR logic gate.

10. The method of claim 2 further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, and each of the first, second, and third transistors having a control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling a second current electrode of the third transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor;

electrically coupling the control electrode of the second transistor to a first input conductor; and

electrically coupling the control electrode of the third transistor to a second input conductor to complete formation of a NAND logic gate.

11. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, and each of the first and second transistors having a control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling a second current electrode of the second transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor; and

electrically coupling the control electrodes of the first and second transistors to an input conductor to complete formation of an inverter logic gate.

12. The method of claim 2 further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, the third transistor having a first and a second control electrode where N is two, and the first and second transistors each having a control electrode;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling a second current electrode of the third transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the second transistor or a first current electrode of the third transistor to an output conductor;

electrically coupling the first control electrode of the third transistor to a first input conductor;

electrically coupling the second control electrode of the third transistor to a second input conductor; and

electrically coupling the either first input conductor to the control electrode of the first transistor and the second input conductor to the control electrode of the second transistor or coupling the second input conductor to the control electrode of the first transistor and the first input conductor to the control electrode of the second transistor to complete formation of a NOR logic gate.

13. The method of claim 2 formed further comprising the steps of:

establishing M equal to three to form a first transistor, a second transistor, and a third transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, the second transistor underlying the third transistor, each of the second and third transistors having a control electrode where N is one for the second and third transistors, and the first transistor having a first and second control electrode where N is two for the first transistor;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling the second current electrode of the third transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor;

electrically coupling the first control electrode of the first transistor to a first input conductor;

electrically coupling the second control electrode of the first transistor to a second input conductor; and

electrically coupling either the first input conductor to the control electrode of the third transistor and the second input conductor to the control electrode of the second transistor or coupling the second input conductor to the control electrode of the third transistor and the first input conductor to the control electrode of the second transistor to complete formation of a NAND logic gate.

14. The method of claim 2 further comprising the steps of:

establishing M equal to two to form a first transistor and a second transistor, each in accordance with the method of claim 2, the first transistor underlying the second transistor, and each of the first and second transistors having a control electrode where N is one;

electrically coupling a first current electrode of the first transistor to a power supply terminal;

electrically coupling a second current electrode of the second transistor to a reference voltage terminal;

electrically coupling either a second current electrode of the first transistor or a first current electrode of the second transistor to an output conductor; and

electrically coupling the control electrodes of the first and second transistors to an input conductor to complete formation of an inverter logic gate.

15. A method for forming a logic device comprising the steps of:

forming a plurality of N rank ordered stacked transistors, where N is an integer greater than one, each transistor except a first transistor thereof overlying a transistor of immediately lower rank, each transistor having a first current electrode, a second current electrode, and a control electrode wherein for each of the stacked transistors either the first current electrode overlies the second current electrode or the second current electrode overlies the first current electrode, each transistor except the first transistor thereof having one of either the first current electrode or the second current electrode electrically coupled to a transistor of immediately lower rank;

further electrically coupling the first and second current electrodes and control electrode of each of the plurality of stacked transistors corresponding to a predetermined logic device structure to form the logic device; and

electrically coupling an output conductor to one current electrode of the N transistors wherein the one current electrode of the N transistors is an electrode other than the second current electrode of the Nth rank ordered transistor and the first current electrode of the first rank ordered transistor.

16. The method of claim 15 wherein the step of further electrically coupling corresponding to a predetermined logic device structure comprises using a logic device structure selected from a group consisting of:

a NAND gate, an inverter, a NOR gate, an exclusive OR gate, an OR gate, and an AND gate.

17. The method of claim 15 wherein the step of further electrically coupling corresponding to a predetermined logic device structure comprises using a logic device structure selected from a group consisting of:

a CMOS gate, a PMOS gate, and an NMOS gate.

18. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises forming at least one of the N rank ordered stacked transistors from a process comprising the steps of:

providing a base layer having a surface;

forming a first dielectric layer overlying the base layer;

forming a control electrode conductive layer overlying the first dielectric layer;

forming a second dielectric layer overlying the control electrode conductive layer;

removing portions of each of the first dielectric layer, the control electrode conductive layer, and the second dielectric layer to form an opening which exposes the surface of the base layer and to form M control electrodes from the control electrode conductive layer, where M is an integer, each of the M control electrodes having a sidewall;

forming a sidewall dielectric laterally adjacent each sidewall of the M control electrodes; and

forming a conductive region within the opening, the conductive region having a first portion which functions as a first current electrode, the first portion being laterally adjacent the first dielectric layer and overlying the base layer, the conductive region having a second portion functioning as a channel region, the second portion being laterally adjacent each sidewall dielectric of the M control electrodes, and overlying the first current electrode, and the conductive region having a third portion functioning as a second current electrode, the third portion being adjacent the second dielectric layer and overlying the channel region.

19. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises:

forming at least one of the N rank ordered stacked transistors by epitaxial growth.

20. The method of claim 19 wherein the step of forming at least one of the N rank ordered stacked transistors by epitaxial growth further comprises:

forming the least one of the N rank ordered stacked transistors by forming a source, a drain, and a channel region by epitaxial growth.

21. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises:

forming a gate dielectric for at least one of the N rank ordered stacked transistors as a sidewall oxide.

22. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises:

forming a gate electrode for at least one of the N rank ordered stacked transistors as a polysilicon layer.

23. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises:

forming M gate electrodes, wherein M is a positive integer, for at least one of the N rank ordered stacked transistors.

24. The method of claim 15 wherein the step of forming the plurality of N rank ordered stacked transistors further comprises:

forming a diffusion region underlying the first transistor of the N rank ordered stacked transistors.

25. A method for forming a semiconductor device comprising the steps of:

providing a substrate having a surface;

forming a first transistor at least partially overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;

forming a second transistor overlying the first transistor and fully overlying the surface of the substrate, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;

forming a conductive interconnect region overlying the substrate, the conductive interconnect region being electrically coupled to the first electrode of the second transistor wherein the conductive interconnect region provides an output voltage from the semiconductor device; and

electrically coupling the first electrode of the second transistor to the second electrode of the first transistor.

26. The method of claim 25 wherein the step of electrically coupling the first electrode of the second transistor to the second electrode of the first transistor further comprises coupling the semiconductor device as a device selected from a group consisting of:

a NAND gate, an inverter, a NOR gate, an exclusive OR gate, an OR gate, and an AND gate.

27. The method of claim 25 wherein the step of electrically coupling the first electrode of the second transistor to the second electrode of the first transistor further comprises coupling the semiconductor device as a device selected from a group consisting of:

a CMOS gate, a PMOS gate, and an NMOS gate.

28. The method of claim 25 wherein each of the steps of forming the first and second transistors comprises:

forming a source, a drain, and a channel region by selective growth.

29. A method for forming a semiconductor device comprising the steps of:

providing a substrate having a surface;

forming a first transistor overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region wherein one of either the first current electrode, the second current electrode, or the channel region is formed by selective growth from the substrate, the first transistor being made of a first conductivity type;

forming a second transistor overlying the first transistor, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region wherein one of either the first current electrode, the second current electrode, or the channel region is formed by selective growth from the substrate, the second transistor being of a second conductivity type;

forming an electrical contact layer overlying the substrate wherein the electrical contact layer is coupled to the second electrode of the first transistor and provides an output voltage which indicates a logic voltage of the second electrode of the first transistor; and

electrically coupling the first electrode of the second transistor to the second electrode of the first transistor.

30. The method of claim 29 wherein the step of electrically coupling further comprises coupling the semiconductor device as a device selected from a group consisting of:

a NAND gate, an inverter, a NOR gate, an exclusive OR gate, an OR gate, and an AND gate.

31. A method for forming a vertically stacked N-input logic device, where N is an integer, the method comprising the steps of:

providing a substrate;

forming a plurality of (N+1) rank ordered stacked transistors overlying the substrate, each transistor except a first transistor thereof overlying a transistor of immediately lower rank, each transistor having a first current electrode, a second current electrode, at least one control electrode, a channel region, and a gate dielectric layer wherein for each of the stacked transistors either the first current electrode overlies the second current electrode or the second current electrode overlies the first current electrode, each transistor except the first transistor thereof having one of either the first current electrode or the second current electrode electrically coupled to a transistor of immediately lower rank;

forming N control electrodes adjacent one of the channel regions of one of the plurality of (N+1) rank ordered stacked transistors; and

electrically coupling the first and second current electrodes and control electrode of each of the plurality of (N+1) rank ordered stacked transistors corresponding to a selected logic device structure to form the vertically stacked N-input logic device.

32. A method for forming at least two transistors, comprising the steps of:

providing a substrate;

forming a first current electrode overlying the substrate;

forming a channel region overlying the first current electrode;

forming a second current electrode overlying the channel region;

forming N gate electrodes adjacent the channel region where N is an integer and is greater than one the first current electrode, second current electrode, channel region, and N gate electrodes forming a first transistor;

forming a second transistor overlying the first transistor wherein the second transistor has a current electrode coupled to the second current electrode of first transistor; and

forming a metallic region which connects the first current electrode of the second transistor to the second current electrode of the first transistor.

33. The method of claim 32 further comprising the step of:

forming a plurality of M stacked transistors where at least one of the M stacked transistors is in accordance with claim 47 and M is an integer greater than one, each of the M stacked transistors having one of two selected conductivity types, each of the M stacked transistors having at least one control electrode, each of the M stacked transistors, except an Mth transistor which overlies all other transistors, having a second current electrode thereof electrically connected to a first current electrode of an immediately overlying transistor.